W48S87-04(1999) Просмотр технического описания (PDF) - Cypress Semiconductor

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W48S87-04
(Rev.:1999)

Spread Spectrum 3 DIMM Desktop Clock

Cypress Semiconductor 

PRELIMINARY

W48S87-04

Overview

The W48S87-04, a motherboard clock synthesizer, can pro-

vide either a 2.5V or 3.3V CPU clock swing, making it suitable

for a variety of CPU options. Twelve SDRAM clocks are pro-

vided in phase with the CPU clock outputs. This provides clock

support for up to three SDRAM DlMMs. Fixed output frequency

clocks are provided for other system functions.

Functional Description

I/O Pin Operation

Pins 2, 7, 8, 25, and 26 are dual-purpose l/O pins. Upon power-

up these pins act as logic inputs, allowing the determination of

assigned device functions. A short time after power-up, the

logic state of these pins is latched and the pins then become

clock outputs. This feature reduces device pin count by com-

bining clock outputs with input select pins.

An external 10-kΩ “strapping” resistor is connected between

each l/O pin and ground or VDD3. Connection to ground sets a

latch to “0”, connection to VDD3 sets a latch to “1”. Figure 1 and

Figure 2 show two suggested methods for strapping resistor

connection.

Upon W48S87-04 power-up, the first 2 ms of operation is used

for input logic selection. During this period, these dual-purpose

I/O pins are three-stated, allowing the output strapping resistor

on each l/O pin to pull the pin and its associated capacitive

clock load to either a logic HIGH or LOW state. At the end of

the 2-ms period, the established logic 0 or 1 condition of each

l/O is pin is then latched. Next the output buffers are enabled,

which converts the l/O pins into operating clock outputs. The

2-ms timer is started when VDD reaches 2.0V. The input bits

can only be reset by turning VDD off and then back on again.

It should be noted that the strapping resistors have no signifi-

cant effect on clock output signal integrity. The drive imped-

ance of both clock outputs is <40Ω (nominal) which is minimal-

ly affected by the 10-kΩ strap to ground or VDD. As with the

series termination resistor, the output strapping resistor should

be placed as close to the l/O pin as possible in order to keep

the interconnecting trace short. The trace from the resistor to

ground or VDD should be kept less than two inches in length

to prevent system noise coupling during input logic sampling.

When the clock outputs are enabled following the 2-ms input

period, target (normal) output frequency is delivered assuming

that VDD has stabilized. If VDD has not yet reached full value,

output frequency initially may be below target but will increase

to target once VDD voltage has stabilized. In either case, a

short output clock cycle may be produced from the CPU clock

outputs when the outputs are enabled.

VDD

Output Strapping Resistor

W48S87-04

Power-on

Reset

Timer

Output

Buffer

Output Three-state

Hold

Output

Low

QD

Data

Latch

10 kΩ

(Load Option 1)

10 kΩ

(Load Option 0)

Series Termination Resistor

22Ω

Clock Load

Figure 1. Input Logic Selection Through Resistor Load Option

Jumper Options

W48S87-04

Power-on

Reset

Timer

Output

Buffer

Output Three-state

Hold

Output

Low

QD

Data

Latch

10 kΩ

VDD

Output Strapping Resistor

Series Termination Resistor

R

Clock Load

Output

Resistor Value R

IOAPIC, SDRAM

39Ω

All other clock outputs

33Ω

Figure 2. Input Logic Selection Through Jumper Option

4

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