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W83176G-733

Dual Bank DDR BUFFER For VIA CHIPSET

Winbond 

W83176R-733/W83176G-733

DUAL BANK DDR BUFFER FOR VIA CHIPSET

7.8 Slew rate reference table

SR<1:0>

10/01

11

00

Normal (default)

Strong

Weak

STATUS

7.9 Register 20: Skew & Slew Rate Control (Default: 8Ah)

BIT

NAME

7 Reserved

6 DDRB_TSKEW<2>

5 DDRB_TSKEW<1>

4 DDRB_TSKEW<0>

3 DDRAT/C0_SR<1>

2 DDRAT/C0_SR<0>

1 DDRAT/C1_SR<1>

0 DDRAT/C1_SR<0>

PWD

1

0

0

0

1

0

1

0

DESCRIPTION

Reserved

DDRB True clock outputs with FB_OUTB True clock

SKEW control bits

DDRAT/C0 slew rate control bits

DDRAT/C1 slew rate control bits

7.10 Register 21: Slew Rate Control (Default: AAh)

BIT

NAME

7 DDRAT/C2_SR<1>

6 DDRAT/C2_SR<0>

5 DDRAT/C3_SR<1>

4 DDRAT/C3_SR<0>

3 DDRAT/C4_SR<1>

2 DDRAT/C4_SR<0>

1 DDRAT/C5_SR<1>

0 DDRAT/C5_SR<0>

PWD

1

0

1

0

1

0

1

0

DESCRIPTION

DDRAT/C2 slew rate control bits

DDRAT/C3 slew rate control bits

DDRAT/C4 slew rate control bits

DDRAT/C5 slew rate control bits

7.11 Register 22: Slew Rate Control (Default: AAh)

BIT

NAME

7 DDRBT/C0_SR<1>

6 DDRBT/C0_SR<0>

5 DDRBT/C1_SR<1>

4 DDRBT/C1_SR<0>

PWD

1

0

1

0

DESCRIPTION

DDRBT/C0 slew rate control bits

DDRBT/C1 slew rate control bits

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