W83195BG-341 Просмотр технического описания (PDF) - Winbond
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W83195BG-341 Datasheet PDF : 26 Pages
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W83195BR-341/W83195BG-341
CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET
5.4 DRAM Buffer
PIN
PIN NAME
45
BUF_IN
46
FBOUT
44,42,38,36,32 DDRT[0:5]
,30
SDRAM
[0,2,4,6,8,10]
43,41,37,35,31 DDRC[0:5]
,29
SDRAM
[1,3,5,7,9,11]
TYPE
DESCRIPTION
IN Reference input from chipset. 2.5V input for DDR only mode.
3.3V for standard SDRAM mode.
OUT Feedback clock for chipset. Output voltage depends on
VDDD
OUT Clock outputs.
SELSD_DD=1, these pins are copies of BUF_IN.
SELSD_DD=0, these pins are copies of BUF_IN.
Voltage depends on the VDDD.
OUT Clock outputs.
SELSD_DD=1, these pins are complementary copies of
BUF_IN.
SELSD_DD=0, these pins are copies of BUF_IN.
Voltage depends on the VDDD.
5.5 I2C Control Interface
PIN
PIN NAME
TYPE
DESCRIPTION
28
SDATA*
I/OD Serial data of I2C 2-wire control interface with internal pull-up
resistor 120K.
27
SCLK*
IN Serial clock of I2C 2-wire control interface with internal pull-up
resistor 120K.
5.6 Output Control Pins
PIN PIN NAME
25 IREF
26 RESET#
TYPE
DESCRIPTION
OUT Deciding the reference current for the CPUT/C pairs. The pin was
connected to the precision resistor tied to ground to decide the
appropriate current. The table is show as follows. TABLE 1
MULTSEL Board Target Reference R, Output
(PIN 11) Trace/ Term Z Iref=VDD/(3*Rr) Current
Ioh @ Z
1
50 Ohms
R=475 1% Ioh=6*Iref 0.7V @ 50
Iref=2.32mA
0
50 Ohms
R=221 1% Ioh=4*Iref 1.0V @ 50
Iref=5mA
OD Select by register 1 bit 6 L_MODE if L_MODE=1 this pin is System
reset signal when the watchdog is time out. This pin will generate
250mS when the watchdog timer is timeout
PD#*
IN Select by register 1 bit 6 L_MODE if L_MODE=0 this pin is Power
Down Function. This is internal 120KΩ pull up.
Publication Release Date: March, 2006
-5-
Revision 1.1
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