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W83194BR-648

CLOCK GENERATOR FOR SIS P4 SERIES CHIPSET

Winbond 

W83194BR-648

5. PIN DESCRIPTION

BUFFER TYPE SYMBOL

IN

INtp120k

INtd120k

OUT

OD

I/O

I/OD

#

*

&

DESCRIPTION

Input

Latched input at power up, internal 120KΩ pull up.

Latched input at power up, internal 120KΩ pull down.

Output

Open Drain

Bi-directional Pin

Bi-directional Pin, Open Drain.

Active Low

Internal 120kΩ pull-up

Internal 120 kΩ pull-down

5.1 Crystal I/O

PIN

PIN NAME

6

XIN

7

XOUT

TYPE

IN

OUT

DESCRIPTION

Crystal input with internal loading capacitors (18pF) and

feedback resistors.

Crystal output at 14.318 MHz nominally with internal loading

capacitors (18pF).

5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs

PIN

40, 39,

44, 43

47

PIN NAME

CPUCLKT_0

CPUCLKC_0,

CPUCLKT_1

CPUCLKC_1,

SDRAM

PCICLK_F0

14

FS3&

PCICLK_F1

15

FS4&

16, 17, 20,

21, 22, 23

PCICLK [0:5]

31, 30 AGPCLK [0:1]

9, 10 ZCLK [0:1]

TYPE

DESCRIPTION

OUT

True CPU clock output and Complementary CPU clock

output. These pins will be stopped by CPU_STOP#

OUT

OUT

INtd120k

OUT

INtd120k

SDRAM clock output, which have syn. or asyn. Frequencies

as CPU clocks. The clock phase is the same as CPUCLKT_0

and CPUCLKT_1.

PCI free running clock during normal operation.

Latched input for FS3 at initial power up for H/W selecting the

output frequency. Internal 120KΩ pull-down

PCI free running clock during normal operation.

Latched input for FS4 at initial power up for H/W selecting the

output frequency. Internal 120KΩ pull-down

OUT Low skew (< 500 pS) PCI clock outputs.

OUT AGP clock outputs for AGP.

OUT Z clock outputs for chipset.

Publication Release Date: April 13, 2005

-3-

Revision 1.1

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