W83194BR-63S Просмотр технического описания (PDF) - Winbond

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W83194BR-63S

STEP-LESS CLOCK FOR SIS CHIPSET

Winbond 

W83194BR-63S

4.3 I2C Control Interface

SYMBOL

PIN

SDATA*

23

SDCLK*

24

I/O

FUNCTION

I/O Serial data of I2C 2-wire control interface

IN Serial clock of I2C 2-wire control interface

4.4 Fixed Frequency Outputs

SYMBOL

PIN

REF0^ / &AGPSEL

2

REF1 ^/ &FS3

3

24_48MHz / &Mode

21

48MHz / &FS0

20

I/O

FUNCTION

14.318MHz reference clock. This REF output is the

I/O atched input for &AGPSEL at initial power up for

H/W selecting the output frequency of AGP clocks.

14.318MHz reference clock.

I/O Latched input for FS3 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

24_48MHz output clock, selected by pin16.

I/O Latched Input. &Mode=0, Pin 27,28,30,31 are

SDRAM clocks; &Mode=1, Pin27,28,29,31 are

CPU_STOP#,SDRAM_STOP#,PCI_STOP#,PD#

48MHz output for USB during normal operation.

I/O Latched input for FS0 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

4.5 Power Pins

SYMBOL

Vdd

VddAGP

VddLCPU

VddP

VddSD

Vdd48

Vss

PIN

FUNCTION

1

Power supply for Ref [0:1] crystal and core logic.

15

Power supply for AGP output, 3.3V.

48

Power supply for CPUCLK[0:3], either 2.5V or 3.3V.

7

Power supply for PCICLK_F, PCICLK[0:4], 3.3V.

43,35,29,25

Power supply for SDRAM[0:12], and CPU PLL core,

nominal 3.3V.

19

Power for 24 & 48MHz output buffers and fixed PLL

core.

4,14,18,19,29,32,39, Circuit Ground.

44

Publication Release Date: May 19, 2005

-5-

Revision 2.0

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