W83194BR-63S Просмотр технического описания (PDF) - Winbond
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W83194BR-63S Datasheet PDF : 16 Pages
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W83194BR-63S
4.2 CPU, SDRAM, PCI ,AGP Clock Outputs
SYMBOL
CPUCLK[0:1]
CPUCS_C2
SDRAM [ 0:7],12
SDRAM 8/PD#
SDRAM9/
SDRAM_STOP#
SDRAM 10/
PCI_STOP#
SDRAM 11/
CPU_STOP#
PCICLK0^/&FS1
PCICLK1^/&FS2
PCICLK [2:4]^
PCICLK5/
RESET#
AGPCLK0/
SEL24#_48*
AGPCLK1/
Mode1*
PIN
47,46
45
42,41,40,38,3
7,36,34,33
31
30
28
27
8
9
10,11,12
13
16
17
I/O
OUT
OUT
FUNCTION
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Powered by VddLCPU. Stopped if CPU_STOP# is
low.
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Powered by VddLCPU. Stopped if CPU_STOP# is
low and Register7 bit7=0.
OUT SDRAM clock outputs.
OUT
OUT
OUT
OUT
I/O
I/O
I/O
I/O
I/O
OUT
Pin21 &Mode=0, SDRAM clock outputs.
Pin21 &Mode=1, PD# input
Pin21 &Mode=0, SDRAM clock outputs.
Pin21 &Mode=1, SDRAM_STOP# input
Pin21 &Mode=0, SDRAM clock outputs.
Pin21 &Mode=1, PCI_STOP# input
Pin21 &Mode=0, SDRAM clock outputs.
Pin21 &Mode=1, CPU_STOP# input
Low skew (< 250ps) PCI clock outputs.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Low skew (< 250ps) PCI clock outputs.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Low skew (< 250ps) PCI clock outputs.
Latched Input. SEL24_48&=0, Pin 21 is 24MHz;
SEL24_48&=1, Pin21 is 48MHz
PCI clock during normal operation. (pin17
Mode1*=1)
If pin17 Mode1*=0, RESET# (open drain, 4ms low
active pulse when Watch Dog time out)
Low skew (< 250ps) AGP clock output.
Latched Input. SEL24#_48*=1, Pin 21 is 24MHz;
SEL24_48*=0, Pin21 is 48MHz
AGP clock outputs
Latched Input. Mode1*=1, Pin 13 is PCICLK;
Mode1*=0, Pin2 is RESET#
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