W83194R Просмотр технического описания (PDF) - Winbond

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W83194R

166MHZ CLOCK FOR SIS CHIPSET

Winbond 

W83194R-630A

PCICLK 1/ *FS2

PCICLK 2/ *MODE

PCICLK [ 3:6 ]

8

9

11,12,13,14

PRELIMINARY

I/O

I/O

OUT

PCI free-running clock during normal operation.

Latched input for FS2 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

PCI clock during normal operation.

Latched input for MODE at initial power up for input

selection of CPU_STOP#, PCI_STOP# and PD#.

When MODE=1, the above pins are SDRAM clock

outputs. When MODE=0, the pins are inputs ACPI

pins.

PCI clock during normal operation.

Low skew (< 250ps) PCI clock outputs.

5.3 I2C Control Interface

SYMBOL

PIN

*SDATA

23

*SDCLK

24

I/O

FUNCTION

I/O Serial data of I2C 2-wire control interface

IN Serial clock of I2C 2-wire control interface

5.4 Fixed Frequency Outputs

SYMBOL

PIN

REF0X2 / *FS3

2

REF1

48

24_48MHz/

25

SEL2.5_3.3#

48MHz / *FS0

26

I/O

FUNCTION

I/O 3.3V, 14.318MHz reference clock output .

Internal 250kΩ pull-up.

Latched input for FS3 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

I/O 3.3V , 14.318MHz reference clock output.

I/O SEL2.5_3.3# controls the Vdd of CPU. If logic 0 at

power on, VddLCPU=3.3V. If logic 1, VddLCPU=2.5

24MHz or 48MHz selected by I2C for Super I/O.

I/O Internal 250kΩ pull-up.

Latched input for FS0 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks. 48MHz output for USB during normal

operation.

Publication Release Date: Nov. 1999

-4-

Revision 0.65

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