W215B Просмотр технического описания (PDF) - Cypress Semiconductor

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W215B

Notebook PC System Frequency Generator for K6 Processors

Cypress Semiconductor 

PRELIMINARY

W215B

Pin Definitions

Pin

Pin Name

No.

PWR_DWN#

44

MODE

VDDQ3

VDDQ2

GND

Reserved

6

7, 15, 21, 25

28, 34, 48

46, 40

3, 10, 17,

24, 31, 37,

43

19, 20

Pin

Type

I

I

P

P

G

I

Pin Description

Power-Down Control: When this input is LOW, device goes into a low-power standby

condition. All outputs are actively held LOW while in power-down. CPU, SDRAM, and

PCI clock outputs are stopped LOW after completing a full clock cycle (2–4 CPU clock

cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full

clock cycle at full operating frequency (3 ms maximum latency).

Mode Control: This input selects the function of device pin 26 (SDRAM7/PCI_STOP#)

and pin 27 (SDRAM6/CPU_STOP#). Refer to description for those pins.

Power Connection: Power supply for PCI0:5, REF0:1, and 48-/24-MHz output buffers.

Connected to 3.3V supply.

Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Connected to

3.3V supply.

Ground Connection: Connect all ground pins to the common system ground plane.

Reserved Pins: Connect to Logic 1.

3

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