IDT723614L20PQFGI(2009) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723614L20PQFGI
(Rev.:2009)
(Rev.:2009)
Integrated Device Technology
IDT723614L20PQFGI Datasheet PDF : 32 Pages
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IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
Commercial
Com'l & Ind'l(1)
Symbol
Parameter
IDT723614L15
Min. Max.
IDT723614L20
Min. Max. Unit
tA
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35
tWFF Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB
tREF Propagation Delay Time, CLKA↑ to EFA and CLKB↑ to EFB
tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to
MBF2 LOW or MBF1 HIGH
2
10
2
12
ns
2
10
2
12
ns
2
10
2
12
ns
2
10
2
12
ns
2
10
2
12
ns
1
9
1
12
ns
tPMR Propagation Delay Time, CLKA↑ to B0-B35(2)and CLKB↑ to A0-A35(3)
tPPE(4) Propagation delay time, CLKB↑ to PEFB
3
11
3
13
ns
2
11
2
12
ns
tMDV Propagation Delay Time, MBA to A0-A35 valid and SIZ1, SIZ0 to B0-B35 valid
1
tPDPE Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
3
tPOPE Propagation Delay Time, ODD/EVEN to PEFA and PEFB
3
tPOPB(5) Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and
2
(B8, B17, B26, B35)
tPEPE Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB,
1
W/RB, SIZ1, SIZ0, or PGB to PEFB
11
1
11. 5 ns
10
3
11
ns
11
3
12
ns
11
2
12
ns
11
1
12
ns
tPEPB(5) Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17,
3
A26, A35); CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35)
tRSF Propagation Delay Time, RST to (MBF1, MBF2) HIGH
1
tEN Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB
2
HIGH to B0-B35 active
12
3
15
1
10
2
13
ns
20
ns
12
ns
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or
1
W/RB LOW to B0-B35 at high-impedance
8
1
9
ns
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Only applies when a new port B bus size is implemented by the rising CLKB edge.
5. Only applies when reading data from a mail register.
COMMERCIAL AND INDUSTRIAL
9
JANUARY 14, 2009
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