IDT723614L20PQFGI(2009) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723614L20PQFGI
(Rev.:2009)
(Rev.:2009)
Integrated Device Technology
IDT723614L20PQFGI Datasheet PDF : 32 Pages
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IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
400
350
fdata = 1/2 fs
TA = 25° C
300
CL = 0 pF
250
200
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
VCC = 5.5V
VCC = 5V
VCC = 4.5V
150
100
50
0
0
10
20
30
40
50
60
70
fs ⎯ Clock Frequency ⎯ MHz
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
80
3146 drw04
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723614 with CLKA and CLKB set
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to
normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with
the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723614 can be calculated by:
PT = VCC x ICC(f) + Σ (CL x VOH2 x fo)
where:
CL
= output capacitance load
fo
= switching frequency of an output
VOH = output high level voltage
When no reads or writes are occurring on the IDT723614, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fs is
calculated by:
PT=VCC x fS x 0.290 mA/MHz
COMMERCIAL AND INDUSTRIAL
7
JANUARY 14, 2009
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