IDT723614L20PQFGI(2009) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723614L20PQFGI
(Rev.:2009)

CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol

ODD/

EVEN

Name

Odd/Even Parity

Select

PEFA

Port A Parity Error

Flag

PEFB

Port B Parity Error

Flag

PGA

Port A Parity

Generation

PGB

Port B Parity

Generation

RST

Reset

SIZ0, SIZ1 Port B Bus Size

Selects

SW0, SW1 Port B byte Swap

Select

W/RA

W/RB

Port A Write/Read

Select

Port B Write/Read

Select

I/O

I

O

(Port A)

O

(Port B)

I

I

I

I

(Port B)

I

(Port B)

I

I

Description

Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when

ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity

generation is enabled for a read operation.

When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as

A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the

parity bit. The type of parity checked is determined by the state of the ODD/EVEN input.

The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate

parity if parity generation is selected by PGA. Therefore, if a mail2 read parity generation is setup

by having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the

A0-A35 inputs.

When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized

as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity

bit. A byte is valid when it is used by the bus size selected for Port B. The type of parity checked is

determined by the state of the ODD/EVEN input.

The parity trees used to check the B0-B35 inputs are shared by the mail 1 register to generate parity if

parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by

having W/RB LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless

of the state of the B0-B35 inputs.

Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is

selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26,

and A27-A35. The generated parity bits are output in the most significant bit of each byte.

Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is

selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,

and B27-B35. The generated parity bits are output in the most significant bit of each byte.

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of

CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and

the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches

the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offsets.

A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following

LOW-to-HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes

can be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for

a port B 36-bit write or read.

At the beginning of each long word transfer, one of four modes of byte-order swapping is selected by

SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-

order swapping is possible with any bus-size selection.

A HIGH selects a write operation and a LOW selects a read operation on for a LOW-to-HIGH port A

transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.

A HIGH selects a write operation and a LOW selects a read operation on for a LOW-to-HIGH port B

B transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.

COMMERCIAL AND INDUSTRIAL

5

JANUARY 14, 2009

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