RS5C62 Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RS5C62

REAL-TIME CLOCK

RICOH Co.,Ltd. 

RP/RF/RS5C62

5.2 Cyclic Interrupt

A desired interrupt cycle can be preset in the bits in the interrupt cycle selection register. With the preset inter-

rupt cycle, the INTR pin is driven low (turned on) to output an request for a cyclic interrupt. A cyclic interrupt can

be output from the INTR pin in the pulse mode and the level mode. In the level mode in particular, a cyclic interrupt

can be disabled by setting the CTFG bit to “0” in the control register 2.

Available interrupt cycles: 6 types (0.488ms, 0.977ms, 7.813ms, 62.5ms, 1s, and 60s)

Available output modes: 2 types (pulse mode and level mode)

• Pulse mode

(The CT3 bit is set to “0”.)

(The CTFG bit is not intended for write

operation.)

• Level mode

(The CT3 bit is set to “1”.)

(The CTFG bit is intended for setting to

“0” only.)

CTFG

INTR

CTFG

INTR

Preset interrupt cycle

Interrupt

(Interrupt) Setting the CTFG bit to “0”

*1) A preset interrupt cycle can be canceled by setting the bits to “0” in the interrupt cycle selection register.

*2) The above figure assumes that a cyclic interrupt occurs in the absence of an alarm interrupt.

*3) The CTFG bit has an inverse logic from that of the INTR pin output.

Cyclic Interrupt

Interrupt cycle selection register

CTFG bit

(See “2.5 Interrupt Cycle Selection Register”)

(See “2.2 Control Register 2”)

6. Timer

Upon lapse of time preset in the timer clock selection register, cyclic pulses are output from the TMOUT pin.

The timer counter can be reset conditional on restart by setting the TMR bit to “1” in the control register 1. (It can

act as a watchdog timer.)

TMOUT

TMFG

MAX.T1

T2

0.244ms

T3

Setting the TMR bit to “1” Setting the TMR bit to “1”

*1) The timer is stopped upon driving low the CE pin input, but restarted upon driving high the CE pin input.

*2) Timer output is disabled upon resetting the TM3 bit to “0” when the stop of oscillation is detected.

*3) The T3 to T1 bits are described in “2. 9 Timer Clock Selection Register”.

*4) Timer output is turned off upon setting the TMR bit to “1” in the control register 1 during timer output.

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