RS5C62 Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RS5C62

REAL-TIME CLOCK

RICOH Co.,Ltd. 

RP/RF/RS5C62

USAGE

1. Reading and Writing Operations

Upon driving high the CE pin, the interfacing input/out-

CE

put pins are enabled, establishing equivalence in logic

A3 to A0

RD

CS

WR

Address

Reading operation

Writing operation

between the RD and CS pin inputs during read opera-

tion and between the WR and CS pin inputs during

write operation. Upon driving low the CE pin, the inter-

facing input/output pins are disabled, preventing occur-

D3 to D0

Data bus

rence of invalid leak current due to their floating. The

CE pin must always be driven either high or low and

must never be left floating.

1.1 Reading Operation

The requirements for reading data from the internal registers and counters are: [1] holding the CE pin high, [2]

performing the process of addressing through the A3 to A0 pin inputs, then [3] driving low the CS pin, [4] causing

the RD pin to transition from its high to low levels, and thereby [5] causing the D3 to D0 pins to output read data.

The reading timing is shown in the chart below.

CE

A0 to A3

CS

RD

or

RD

CS

D0 to D3

(Read Data)

[1]

tCES [2]

[3]

tAS(RD)

[4]

tRR

[5]

tAH(RD)

tCEH

tRZ

Valid

*1) The CS and RD pin inputs are interchangeable. The diagonally shaded sections marked in the above timing chart may be set to both high and low

levels. (Consequently, the CS and RD pin inputs may be caused to transition from their high to low levels before the process of addressing.)

*2) “tAS (RD)” indicates the time required to perform the process of addressing before the start of read operation at which both the RD and CS pin inputs

are driven low.

*3) “tAH (RD)”indicates the time required to maintain the result of addressing after the completion of read operation at which either the RD or CS pin input

is driven high.

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