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IDT723613L30PF

CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36

COMMERCIAL TEMPERATURE RANGES

CLKA

CSA LOW

tCLK

tCLKH tCLKL

WRA HIGH tENS

MBA

ENA

tENS

tENH

tENH

FF HIGH tDS

tDH

A0 - A35

CLKB

EF

W1

tSKEW1 (1)

tCLK

tCLKH tCLKL

1

FIFO Empty

2

tREF

tREF

CSB LOW

W/RB LOW

SIZ1,

SIZ0 LOW

tENS

tENH

ENB

B0 -B35

tA

W1

3145 drw 09

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.

2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EF is set LOW by the last word or byte

read from the FIFO, respectively.

Figure 9. EF Flag Timing and First Data Read when the FIFO is Empty

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