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IDT723613L30PF

CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36

COMMERCIAL TEMPERATURE RANGES

empty+2. The almost-empty state is defined by the value of

the almost-full and almost-empty offset register (X). This

register is loaded with one of four preset values during a

device reset (see reset above). The almost-empty flag is LOW

when the FIFO contains X or less long words in memory and

is HIGH when the FIFO contains (X+1) or more long words.

Two LOW-to-HIGH transitions on the port B clock (CLKB)

are required after a FIFO write for the almost-empty flag to

reflect the new level of fill. Therefore, the almost-empty flag

of a FIFO containing (X+1) or more long words remains LOW

if two CLKB cycles have not elapsed since the write that filled

the memory to the (X+1) level. The almost-empty flag is set

HIGH by the second CLKB LOW-to-HIGH transition after the

FIFO write that fills memory to the (X+1) level. A LOW-to-

HIGH transition of CLKB begins the first synchronization cycle

if it occurs at time tSKEW2 or greater after the write that fills the

FIFO to (X+1) long words. Otherwise, the subsequent CLKB

cycle can be the first synchronization cycle (see Figure 11).

ALMOST FULL FLAG (AF)

The FIFO almost-full flag is synchronized to the port

clock that writes data to its array (CLKA). The state machine

that controls an almost-full flag monitors a write-pointer and

read-pointer comparator that indicates when the FIFO SRAM

status is almost full, almost full-1, or almost full-2. The almost-

full state is defined by the value of the almost-full and almost-

empty offset register (X). This register is loaded with one of

four preset values during a device reset (see reset above).

The almost-full flag is LOW when the FIFO contains (64-X) or

more long words in memory and is HIGH when the FIFO

contains [64-(X+1)] or less long words.

Two LOW-to-HIGH transitions on the port A clock (CLKA)

are required after a FIFO read for the almost-full flag to reflect

the new level of fill. Therefore, the almost-full flag of a FIFO

containing [64-(X+1)] or less words remains LOW if two CLKA

cycles have not elapsed since the read that reduced the

number of long words in memory to [64-(X+1)]. The almost-

full flag is set HIGH by the second CLKA LOW-to-HIGH

transition after the FIFO read that reduces the number of long

words in memory to [64-(X+1)]. A LOW-to-HIGH transition on

CLKA begins the first synchronization cycle if it occurs at time

tSKEW2 or greater after the read that reduces the number of

long words in memory to [64-(X+1)]. Otherwise, the subse-

quent CLKA cycle can be the first synchronization cycle (see

Figure 12).

MAILBOX REGISTERS

Two 36-bit bypass registers (mail1, mail2) are on the

IDT723613 to pass command and control information be-

tween port A and port B without putting it in queue. A LOW-to-

HIGH transition on CLKA writes A0-A35 data to the mail1

register when a port A write is selected by CSA, W/RA, and

ENA (with MBA HIGH). A LOW-to-HIGH transition on CLKB

writes B0-B35 data to the mail2 register when a port B write is

selected by CSB, W/RB, and ENB (and both SIZ0 and SIZ1

are HIGH). Writing data to a mail register sets its correspond-

ing flag (MBF1 or MBF2) LOW. Attempted writes to a mail

register are ignored while its mail flag is LOW.

When the port B data (B0-B35) outputs are active, the

data on the bus comes from the FIFO output register when

either one or both SIZ1 and SIZ0 are LOW and from the mail1

register when both SIZ1 and SIZ0 are HIGH. The mail1

register flag (MBF1) is set HIGH by a rising CLKB edge when

a port B read is selected by CSB, W/RB, and ENB, (and both

SIZ1 and SIZ0 HIGH). The mail2 register flag (MBF2) is set

HIGH by a rising CLKA edge when a port A read is selected

by CSA, W/RA, and ENA (with MBA HIGH). The data in a mail

register remains intact after it is read and changes only when

new data is written to the register.

DYNAMIC BUS SIZING

The port B bus can be configured in a 36-bit long word,

18-bit word, or 9-bit byte format for data read from the FIFO.

Word- and byte-size bus selections can utilize the most

significant bytes of the bus (big endian) or least significant

bytes of the bus (little endian). Port B bus-size can be

changed dynamically and synchronous to CLKB to commu-

nicate with peripherals of various bus widths.

The levels applied to the port B bus-size select (SIZ0,

SIZ1) inputs and the big-endian select (BE) input are stored

on each CLKB LOW-to-HIGH transition. The stored port B

bus-size selection is implemented by the next rising edge on

CLKB according to Figure 1.

Only 36-bit long-word data is written to or read from the

FIFO memory on the IDT723613. Bus-matching operations

are done after data is read from the FIFO RAM. Port B bus

sizing does not apply to mail register operations.

BUS-MATCHING FIFO READS

Data is read from the FIFO RAM in 36-bit long-word

increments. If a long-word bus-size is implemented, the entire

long word immediately shifts to the FIFO output register upon

a read. If byte or word size is implemented on port B, only the

first one or two bytes appear on the selected portion of the FIFO

output register, with the rest of the long word stored in auxiliary

registers. In this case, subsequent FIFO reads with the same

bus-size implementation output the rest of the long word to the

FIFO output register in the order shown by Figure 1.

Each FIFO read with a new bus-size implementation

automatically unloads data from the FIFO RAM to its output

register and auxiliary registers. Therefore, implementing a

new port B bus-size and performing a FIFO read before all

bytes or words stored in the auxiliary registers have been read

results in a loss of the unread data in these registers.

When reading data from FIFO in byte or word format, the

unused B0-B35 outputs remain inactive but static, with the

unused FIFO output register bits holding the last data value to

decrease power consumption.

BYTE SWAPPING

The byte-order arrangement of data read from the FIFO

can be changed synchronous to the rising edge of CLKB.

Byte-order swapping is not available for mail register data.

Four modes of byte-order swapping (including no swap) can

be done with any data port size selection. The order of the

bytes are rearranged within the long word, but the bit order

within the bytes remaines constant.

11

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