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IDT723613L30PQF Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723613L30PQF
IDT
Integrated Device Technology IDT
IDT723613L30PQF Datasheet PDF : 29 Pages
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
CLKB
EF HIGH
CSB
W/RB
ENB
SW1,
SW0
tSZS
BE
tENS
tSWS
tSZH
tENH
tSWH
SIZ1,
SIZ0
PGB,
ODD/
EVEN
B0-B8
tSZS
tSZH
(1,0)
(1,0)
Not (1,1)(1)
tPGS
(1,0)
Not (1,1)(1)
tPGH
(1,0)
Not (1,1) (1)
tEN
tA
Previous Data
tA
Read 1
tA
Read 2
tA
tA
tA
B27-B35
Previous Data
Read 1
Read 2
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused bytes hold last FIFO output register data for byte-size reads.
DATA SWAP TABLE FOR FIFO BYTE READS
FIFO DATA WRITE
A35-A27 A26-A18
A17-A9
A8-A0
SWAP MODE
SW1
SW0
A
B
C
D
L
L
A
B
C
D
L
H
A
B
C
D
H
L
A
B
C
D
H
H
Figure 8. FIFO Byte Read-Cycle Timing
COMMERCIAL TEMPERATURE RANGES
No Operation
Not (1,1) (1)
tA
Read 3
tA
Read 3
tDIS
Read 4
tDIS
Read 4
3145 drw 08
READ
NO.
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
FIFO DATA READ
BIG
ENDIAN
B35-B27
A
B
C
D
LITTLE
ENDIAN
B8-B0
D
C
B
A
D
A
C
B
B
C
A
D
C
B
D
A
A
D
B
C
B
C
A
D
D
A
C
B
19

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