IDT723613L30PF Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
Список матч
IDT723613L30PF
Integrated Device Technology
IDT723613L30PF Datasheet PDF : 29 Pages
| |||
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
TABLE 3: PORT B ENABLE FUNCTION TABLE
CSB W/RB ENB SIZ1, SIZ0 CLKB
H
X
X
X
X
L
H
L
X
X
L
H
H One, both LOW ↑
L
H
H
Both HIGH
↑
L
L
L One, both LOW X
L
L
H One, both LOW ↑
L
L
L
Both HIGH
X
L
L
H
Both HIGH
↑
B0-B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO output regisger
Active, FIFO output register
Active, mail1 register
Active mail1 register
PORT FUNCTION
None
None
None
Mail2 write
None
FIFO read
None
Mail1 read (set MBF1 HIGH)
EMPTY FLAG (EF)
The FIFO empty flag is synchronized to the port clock
that reads data from its array (CLKB). When the empty flag
is HIGH, new data can be read to the FIFO output register.
When the empty flag is LOW, the FIFO is empty and at-
tempted FIFO reads are ignored. When reading the FIFO with
a byte or word size on port B, EF is set LOW when the fourth
byte or second word of the last long word is read.
The FIFO read pointer is incremented each time a new
word is clocked to its output register. The state machine that
controls the empty flag monitors a write-pointer and read-
pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. A word written to the
FIFO can be read to the FIFO output register in a minimum of
three port B clock (CLKB) cycles. Therefore, an empty flag is
LOW if a word in memory is the next data to be sent to the FIFO
output register and two CLKB cycles have not elapsed since
TABLE 4: FIFO FLAG OPERATION
NUMBER OF 36-BIT
WORDS IN THE FIFO (1)
SYNCHRO-
NIZED
TO CLKB
EF AE
SYNCHRO-
NIZED
TO CLKA
AF FF
0
L
L
H
H
1 to X
H
L
H
H
(X+ 1) to [64 - (X + 1)]
H
H
H
H
(64 - X) to 63
H
H
L
H
64
H
H
L
L
NOTE:
1. X is the value in the almost-empty flag and almost-full flag offset register
the time the word was written. The empty flag of the FIFO is
set HIGH by the second LOW-to-HIGH transition of CLKB,
and the new data word can be read to the FIFO output register
in the following cycle.
A LOW-to-HIGH transition on CLKB begins the first
synchronization cycle of a write if the clock transition occurs at
time tSKEW1 or greater after the write. Otherwise, the subse-
quent CLKB cycle can be the first synchronization cycle (see
Figure 9).
FULL FLAG (FF)
The FIFO full flag is synchronized to the port clock that
writes data to its array (CLKA). When the full flag is HIGH, a
SRAM location is free to receive new data. No memory
locations are free when the full flag is LOW and attempted
writes to the FIFO are ignored.
Each time a word is written to the FIFO, its write-pointer
is incremented. The state machine that controls the full flag
monitors a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from the FIFO, its previous
memory location is ready to be written in a minimum of three
CLKA cycles. Therefore, a full flag is LOW if less than two
CLKA cycles have elapsed since the next memory write
location has been read. The second LOW-to-HIGH transition
on the full flag synchronizing clock after the read sets the full
flag HIGH and data can be written in the following clock cycle.
A LOW-to-HIGH transition on CLKA begins the first
synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subse-
quent clock cycle can be the first synchronization cycle (see
Figure 10).
ALMOST-EMPTY FLAG (AE)
The FIFO almost empty-flag is synchronized to the port
clock that reads data from its array (CLKB). The state machine
that controls the almost-empty flag monitors a write-pointer
and read-pointer comparator that indicates when the FIFO
SRAM status is almost empty, almost empty+1, or almost
10
Share Link: