CDP1882 Просмотр технического описания (PDF) - Intersil

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CDP1882

CMOS 6-Bit Latch and Decoder Memory Interfaces

Intersil 

CDP1881C, CDP1882, CDP1882C

WAIT

CLR

CDP1882

LATCH/

DECODER

CS3

CLK

CS2

CE

CS1

CS0

MA0 - MA5

A8 - A11

TO OTHER

CHIP SELECTS

ADDRESS BUS

TPA

CDP1800

SERIES

CPU

ADDRESS BUS

MRD

MWR

A8 - A11

CS2

A0 - A7

CDM5332

4K x 8

ROM

CSI/OE

A8 - A10

CE

A0 - A7

CDM6116A

2K x 8

RAM

OE

WE

WAIT

CLR

DATA BUS

FIGURE 5. CDP1800-SERIES SYSTEM USING THE CDP1882

CDP1882

LATCH/

DECODER

CS3

CLK CS2

CE

CS1

CS0

MA0 - MA5

A8 - A11

ADDRESS BUS

TPA

CDP1800

SERIES

CPU

ADDRESS BUS

MRD

A8 - A11

CS2

A0 - A7

CDM5332

4K x 8

ROM

CSI/OE

A8 - A11

CS2

A0 - A7

CDM5332

4K x 8

ROM

CSI/OE

A8 - A11

CS2

A0 - A7

CDM5332

4K x 8

ROM

CSI/OE

DATA BUS

FIGURE 6. 6K-BYTE ROM SYSTEMS USING THE CDP1882

A8 - A11

CS2

A0 - A7

CDM5332

4K x 8

ROM

CSI/OE

4-7

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