PI6C110EV Просмотр технического описания (PDF) - Pericom Semiconductor
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PI6C110EV Datasheet PDF : 15 Pages
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PI6C110E
Clock Solution for 133 MHz
11223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900C112211e22l33e44r5566o77n8899/00P1122e33n4455t66i77u88m99001122I33I44/55I66I7788I9900P11r2211o22c3344e55s66s7788o99r00s1122
AC Timing Notes:
1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.
2. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
4. TLOW is measured at 0.4V for all outputs.
5. The time specified is measured from when the power supply achieves its nominal operating level
(typical condition VDD3.3V = 3.3V) until the frequency output is stable and operating within specification.
6. TRISE and TFALL are measured as a transition through the threshold region
VOL = 0.4V and VOH = 2.0V (1mA) JEDEC Specification.
7. The average period over any 1µs period of time must be greater than the minimum specified period.
Group Skew And Jitter Limits
Output
Group
Pin-pin
Skew
MAX.
Cycle-Cycle
Jitter
CPU
175ps
250ps
SDRAM 250ps
250ps
APIC
250ps
500ps
48 MHz N/A
500ps
3V66
175ps
500ps
PCI
500ps
500ps
REF
N/A
1000ps
Duty Cycle
45/55
45/55
45/55
45/55
45/55
45/55
45/55
Nom VDD
2.5V
3.3V
2.5V
3.3V
3.3V
3.3V
3.3V
Skew, jitter
measure point
1.25V
1.5V
1.25V
1.5V
1.5V
1.5V
1.5V
OOuuttppuutt
Buffer
Test Point
OCultopcuktOWuatpvuetfoWrmave
Test Load
Tperiod
Duty Cycle
2.0
2.5V Clocking 1.25
Interface 0.4
THIGH
TLOW
TRISE
TFALL
Tperiod
Duty Cycle
2.4
3.3V Clocking 1.5
Interface 0.4
THIGH
TLOW
TRISE
TFALL
Figure 1.
6
PS8410
08/11/99
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