PI6C110EV Просмотр технического описания (PDF) - Pericom Semiconductor
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PI6C110EV Datasheet PDF : 15 Pages
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PI6C110E
Clock Solution for 133 MHz
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Power Management
Maximum Current
Condition
Power Down Mode
(PWRDWN#) = 0)
Max. 2.5 supply consumption,
Max. discreet cap loads,
VDD2.5 = 2.625V
All static inputs = VDD3.3 or VSS
100µA
Max. 3.3 supply consumption,
Max. discreet cap loads,
VDD3.3 = 3.465V,
All static inputs = VDD3.3 or VSS
200µA
CPU = 66 MHz, SDRAM = 100 MHz
SEL [0-2] = 010
70mA
280mA
CPU = 100 MHz, SDRAM = 100 MHz
SEL [2-0] = 011
100mA
280mA
CPU = 133 MHz, SDRAM = 133 MHz
SEL [2-0] = 110
TBD
TBD
CPU = 133 MHz, SDRAM = 100 MHz
SEL [2-0] = 111
TBD
TBD
Power Management
Signal
Signal State
Latency
No. of rising edges of PCI Clocks
PWRDWN# 1 (normal operation)
3ms
0 (power down)
See Timing Diagram Below
Notes:
1. Clock on/off latency is defined in the number of rising edges of free running PCI clock
between the clock disable goes low/high to the first valid clock comes out of the device.
2. Power up latency is when PWRDWN# goes inactive (high) to when the first valid clocks
are driven from the device.
The power down selection is used to put the part into a very low
power state without turning off the power to the part. PWRDWN#
is an asynchronous active low input. This signal is synchronized
internal to the device prior to powering down the clock synthesizer.
PWRDWN# is an asynchronous function for powering up the
system. Internal clocks are not running after the device is put in
power down. When PWRDWN# is active low all clocks are driven
to a low value and held prior to turning off the VCOs and the crystal.
The power -up latency needs to be less than 3ms. The REF and
48 MHz clocks are expected to be stopped in the LOW state as soon
as possible. Due to the state of the internal logic, stopping and
holding the REF clock outputs in the LOW state may require more
than one clock cycle to complete.
10
PS8410
08/11/99
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