STK12C68-C45 Просмотр технического описания (PDF) - Cypress Semiconductor
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STK12C68-C45 Datasheet PDF : 20 Pages
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Pin Configurations
Figure 1. 28-Pin SOIC/DIP and LLC
STK12C68
Pin Definitions
Pin Name Alt
IO Type
Description
A0–A12
DQ0-DQ7
WE
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
CE
E
OE
G
Input
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
VCC
HSB
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
VCAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-51027 Rev. **
Page 2 of 20
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