STK12C68-C45 Просмотр технического описания (PDF) - Cypress Semiconductor
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STK12C68-C45 Datasheet PDF : 20 Pages
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STK12C68
SRAM Write Cycle
Parameter
Cypress
Parameter
Alt
tWC
tAVAV
tPWE
tWLWH, tWLEH
tSCE
tELWH, tELEH
tSD
tDVWH, tDVEH
tHD
tWHDX, tEHDX
tAW
tAVWH, tAVEH
tSA
tAVWL, tAVEL
tHA
tHZWE [9,10]
tLZWE [9]
tWHAX, tEHAX
tWLQZ
tWHQX
Switching Waveforms
ADDRESS
CE
WE
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
25 ns
Min Max
25
20
20
10
0
20
0
0
10
5
35 ns
Min Max
35
25
25
12
0
25
0
0
13
5
45 ns
Unit
Min Max
45
ns
30
ns
30
ns
15
ns
0
ns
30
ns
0
ns
0
ns
14 ns
5
ns
Figure 9. SRAM Write Cycle 1: WE Controlled [11, 12]
tWC
tSCE
tHA
tAW
tSA
tPWE
DATA IN
DATA OUT
ADDRESS
PREVIOUS DATA
tHZWE
tSD
DATA VALID
HIGH IMPEDANCE
tHD
tLZWE
Figure 10. SRAM Write Cycle 2: CE Controlled [11, 12]
tWC
tSA
tSCE
tHA
CE
WE
DATA IN
tAW
tPWE
tSD
tHD
DATA VALID
DATA OUT
HIGH IMPEDANCE
Notes
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
11. HSB must be high during SRAM Write cycles.
12. CE or WE must be greater than VIH during address transitions.
Document Number: 001-51027 Rev. **
Page 10 of 20
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