STK12C68-5 Просмотр технического описания (PDF) - Cypress Semiconductor
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STK12C68-5 Datasheet PDF : 18 Pages
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STK12C68-5 (SMD5962-94599)
SRAM Write Cycle
Parameter
Cypress
Parameter
Alt
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE [9,10]
tLZWE [9]
tAVAV
tWLWH, tWLEH
tELWH, tELEH
tDVWH, tDVEH
tWHDX, tEHDX
tAVWH, tAVEH
tAVWL, tAVEL
tWHAX, tEHAX
tWLQZ
tWHQX
Switching Waveforms
ADDRESS
CE
WE
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
35 ns
Min
Max
35
25
25
12
0
25
0
0
13
5
55 ns
Min
Max
55
45
45
25
0
45
0
0
15
5
Figure 10. SRAM Write Cycle 1: WE Controlled [11, 12]
tWC
tSCE
tHA
tAW
tSA
tPWE
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA IN
DATA OUT
ADDRESS
PREVIOUS DATA
tHZWE
tSD
DATA VALID
HIGH IMPEDANCE
tHD
tLZWE
Figure 11. SRAM Write Cycle 2: CE Controlled [11, 12]
tWC
tSA
tSCE
tHA
CE
WE
DATA IN
tAW
tPWE
tSD
tHD
DATA VALID
DATA OUT
HIGH IMPEDANCE
Notes
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
11. HSB must be high during SRAM Write cycles.
12. CE or WE must be greater than VIH during address transitions.
Document Number: 001-51026 Rev. **
Page 10 of 18
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