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MC141622P

Advanced Comb Filter-II (ACF-II)

Motorola => Freescale 

Figure 2 shows the 1/0 signals of the Advanced Comb Filter-Il.

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INTRODUCTION

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The Advanced Comb Filter-n (ACF-ll)i~:$~&-petior-

mance HCMOS digital filter with built–i~;w~~fid D/A con-

verters. The basic function of the chip +,,th~:s~paration of the

Luminance Y and Chrominance ~’~ig~t~ from the NTSC

composite video signal. The A~.-~i@*imizes the problems

often generated by Y/C sep$~ti$ such as dot+rawl and

cross-color. It uses a 1~&&

clock that allows an ex-

tended frequency ban@w;%~~deo signal to be input. This

Y/C separation is r~~~d by the digital advanced comb fil-

ters. The built–in 4Xp&@L circuit allows a subcarrier signal

input, from whi~~~.:~fsc clock is generated for video signal

processingqLw~~&lows a video signal input of an extended

frequenqy~~~wldth. The built–in vertical enhancer circuit

can en~nc$ {he Luminance Y signal. The built–in ND and

D/+J~~&~$Rers allow easy connection to analog video cir-

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ADVANCED COMB FILTER-II DESCRIPTION

The simplified block diagram of the Advanced Comb

Filter–11 chip is shown at the beginning of this data sheet.

There are five major functions represented in this block dia-

gram. The first block is the MD conversion block. ‘The high

speed 8–bit binary analog–to~igital converter conveds the

incoming analog video signal to an 8–bit bina~ data stream.

The conversion frequency is 14.3 MHz which is four times

the color subcarrier frequency,

MC141 622

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The second block contains the Advanced Comb Filter-n

algorithm. The digital data from the ND converter is pro-

cessed by the algorithm of the Advanced Comb Filter-Il. The

composite video is filtered by the band–pass filter (BPF) and

separated into the Luminance Y and Chrominance C signals.

The third block is the vetical enhancer circuit block. This

vertical enhancer emphasizes the picture outline of the vetii-

cal direction.

The fourth block is the digital-to–analog conversion block.

Two 8–bit D/A converters convert the Iurninance and chromi-

nance into analog outputs. The conversion frequency is four

times the subcarrier signal (14.3 MHz). The chrominance

analog output is biased with a dc offset of half the value of the

DA converter reference.

The fifth block is a 4xfsc CLK generation circuit. This block

generates four times the subcarrier signal and phase locks

the, inputting subcarrier on FSC pin.

ND Converter

The composite video signal input is converted to the digital

code by the h’igh speed 8–bit ND converter, The ND con-

verter reference has a self–bias function which generates

VTp = 4.6 V, VBT = 1.55 V. This allows the MD converter to

function without an external reference circuit.

Clamp Voltage Regulating Circuit

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The clamp voltage regulating circuit sync tip clamps the in-

put signal when the ~n pin is connected to the CLout pin and —

the video signal is input using ac coupling. It compares the

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MOTOROLA

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