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MC141622P

Advanced Comb Filter-II (ACF-II)

Motorola => Freescale 

OPERATING MODES

The Advanced Comb Filter-n can be operated in any of

four modes. These modes are fixed by a digital code input

into MODEO and MODEI. The descriptions of the four types

of operating modes are:

Table 3. Operating MODE Switching Function

I

Mode

I MODE1 I MODEO I

I Normal (fsc) Mode

lLlLl”-

Normal (4xfsc) Mode

L

H

Normal (fsc) Mode

/

This mode is for the normal Y/C separation, The video sig-

nal input to the ND converter is separated into its Y and C

components and output as a,nalog information from the D/A

convetier outputs. The clamp circuit operates as sync tip

clamp by connecting CLout with ~n, and clamps the input

video signal to the fixed value $04. The coring characteristics

of the vertical enhancer circuit can be set up on the digital

port. This mode is used when an NTSC color subcarrier is

used to generate a 4xfsc using the internal PLL.

Normal (4xfsc) Mode

This mode is for the normal Y/C separation. The video sig-

nal input to the WD converter is separated into its Y and C

components and output as analog information from the D/A

converter outputs. The clamp circuit operates as sync tip

clamp by connecting CLout,with ~n, and clamps the input vid-

eo signal to the fixed value $04, The coring characteristics of

the vertical enhancer circuit can be setup on the digital port.

In this mode an external 4xfsc CLK is input on the FSC pin.

Digital Input Comb Filtering Mode

In this mode, the comb filter is used as two separate

blocks; the WD converter portion, and the filter and D/A por-

tion. This mode can r+input and filter converted digital data

outputs by the ND converter after arbitrarily being digitally

processed by external circuits, The converted digital d~

out~uts into CO – C7, Moreover, the data input into DO–,BT{s

filtered by the ACF-11 algofithrn, and is output as a~f@~~~9

signal from Yout and Cout. The two blocks can o~~[gt*Nde-

pendently with different frequency and phase #<~~W~i~nals.

The CLK(AD) pin is the clock input to the fl&~*~Rer

block

and the CLK pin the clock source (4xfsc)JoFl~%@ler and D/A

converters. At this time, the clamp ci$~~%,~@?ksas sync tip

clamp when CLout is connected to V~ a~d clamps the input

video signal to the internally fixe~~~~$~~Value ($04).

,:~.,,::+x.,..*..+‘..:,k+‘1+* ~’

Digital Output Comb Filtetiq~ ~ode

This mode outputs Q~(tals’b~ues of the luminance and

chrominance signals.~*:@&kSion to functioning as a standard

analog output Y/C %raf$r. This allows arbitray digital pro-

cessing of the fig~i~~~tessed Y and C digital outputs by an

external circ@tt$k~~titetiaces with an analog circuit easily,

since bot~%~~~ Y and C signals are output at “the same

time. ,,-:*:/$“:’!i:$~.f.},,??;}

Thej~& signal input to the WD converter is converted to

di@:~#~, and forwarded to the filter portion. The Y/C sepa-

rat~data from the filter portion is output from Youf and Cout

after the D/A conversion. At the same time, the filter portion

output is also forwarded to the digital interface and the lumi-

nance digital value is output from CO - C7 and the chromi-

nance digital value is output from DO - D7, With this mode,

the clamp circuit works as a sync tip clamp with CLout

connected to ~n, and clamps the input video signal internally

to the fixed digital value ($04). This mode operates with an

external 4xfsc CLK which is input on the FSC pin.

~

Table 3 shows the relationship between the MODE pin and

MODE’condition.

Digital Input Comb Rltering Mode

Digital Output Comb Rltering Mode

H

,L

H

H

APPLICATION

VCC, GND

TO maximize

DESIGN CONSIDERATIONS

“’:\.:$,“,(

.,l~..~,:*.?$...>.~.t~...’,J.:,.?,:,.:\$.:,,<.h*;<>.,\:;:.

the performance of the MCI 41 ~~~,.~>~

should be kept to a minimum. Good printed ~~~~%~~oard

design will enhance the operation of the MQ#~%~,#. Sepa-

rate analog and digital grounds will reduce nw~.and conver-

sion errors. In addition, separate filter~.~~~ti?og VCC and

digital VDD will also help to minimize n“wand conversion

er~ors. ~u%cient decoupling

prove performance.

an~~$:a‘~,sr.tt(:.,.,:~..>(,!,.l:e$a, ds will also im-

When designing mixed’~~~l~g)digital

printed circuit

boards, separate ground~@@%r digital ground and analog

ground should be em,~~oy~~.,Large switching currents gener-

ated by digital cir~fiq;,~~ll be amplified by analog circuitry

and can quickly @@~;~ &rcuit unusable, Care should be tak-

en to ensure,,~fi~lo$ ground does not inadvetiently become

part of the ‘*taI” ground. The analog and digital grounds

should,@ cotikcted together at only one point. This is usu-

ally d:o~’~ar where power enters the printed circuit board.

Adt:i~~ially, when interconnecting several printed circuit

..,~~,>J~,~{.~.,.~Xo*.g{ether, care must be taken to ensure that cabling

‘~~as not interconnect digital and analog grounds together to

,<, produce a path for digital switching currents through analog

—

ground,

When using any device with the performance and speed of

—

the MC141 622, ground planes are essential. Loosely inter-

connected traces and/or random areas of ground strewn

around the printed circuit board are inadequate for high per-

formance circuitry. While distribution of VDD and VCC can be

done by bussing, to do so with the ground system is

disastrous.

A l–inch long conductor is an 18 nH inductor. The cross

sectional area of the conductor affects the exact value of the

inductance, but for most PCB traces thiy is approximately

correct. If the ground system is composed of traces or

clumps of ground loosely interconnected, it will be inductive.

The amount of inductance will be proportional to the length of

the conductors making up the ground. This inductance can-

not be decoupled away. It must be designed out.

A CMOS device exhibits a characteristic input capacitance

of about 10 pF. If this gate is driven by a digital signal that

switches 2,5 V in a period of 5 ns, the equation for the aver-

age current flowing during the switching time will be:

IAV = Cdvldt.

A voltage change of 2,5 V in 5 ns requires an average cur-

rent of 5 mA. If we assume a linear ramp statiing from zero,

the total change in current will be 10 mA. The change in cur-

rent per nanosecond per gate can be found by dividing the

change in current by the time

10 mW5 ns = 2 m~ns.

For a device with 16 outputs driving one gate for each

output,

di/dt = 16x 2 mWns = 32 m~ns.

MC141 622

10

MOTOROLA

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