CLK(AD)
AD INPUT
—
OUTPUT DATA
(co- C7)
CLOCK
INPUT DATA
(DO- D7)
Figure
1b. Digital
Signal
Input Timing
Diagram
,?+.,
,$~’
.5,$,
(Duri@’”~ital Input Comb
..t~~$:.tJ.\>\:,:>.,i;,\
Filtering
Mode)
—
—
“Clamp Mode Output Voltage, VCIY (Non-input when connecting ~n - CLout)
Vcly = (VTp - VET) (N+ 1)/ 256+ VBT f 50 mV
where N = Clamp Code Input (N c 255)
q If the calculated value of the output voltage, VCIY > VCIYS,then VCIY = VCIYS
q Clamp Value N is fixed, N = 4.
MC141 622
6
—
—
MOTOROLA