CS8405A-CZ(2002) Просмотр технического описания (PDF) - Cirrus Logic
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CS8405A-CZ Datasheet PDF : 36 Pages
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CS8405A
7. CONTROL PORT REGISTER SUMMARY
Addr
Function
0 Reserved
1 Control 1
2 Control 2
3 Data Flow Control
4 Clock Source Control
5 Serial Input Format
6 Reserved
7 Interrupt 1 Status
8 Interrupt 2 Status
9 Interrupt 1 Mask
A Interrupt 1 Mode (MSB)
B Interrupt 1 Mode (LSB)
C Interrupt 2 Mask
D Interrupt 2 Mode (MSB)
E Interrupt 2 Mode (LSB)
F-11 Reserved
12 CS Data Buffer Control
13 U Data Buffer Control
1E-1D Reserved
1F-37 C or U Data Buffer
7F ID and Version
7
0
0
0
0
0
SIMS
0
TSLIP
0
TSLIPM
TSLIP1
TSLIP0
0
0
0
0
0
0
0
ID3
6
0
VSET
0
TXOFF
RUN
SISF
0
0
0
0
0
0
0
0
0
0
0
0
0
ID2
5
0
0
0
AESBP
CLK1
SIRES1
0
0
0
0
0
0
0
0
0
0
BSEL
0
0
ID1
4
0
MUTEAES
0
0
CLK0
SIRES0
0
0
0
0
0
0
0
0
0
0
0
UD
0
ID0
3
0
0
0
0
0
SIJUST
0
0
0
0
0
0
0
0
0
0
0
UBM1
0
VER3
2
0
INT1
MMT
0
0
SIDEL
0
0
EFTU
0
0
0
EFTU
M
EFTU1
EFTU0
0
EFTCI
UBM0
0
VER2
1
0
INT0
MMCST
0
0
SISPOL
0
EFTC
0
EFTCM
EFTC1
EFTC0
0
0
0
0
CAM
0
0
VER1
0
0
TCBLD
MMTLR
0
0
SILRPOL
0
0
0
0
0
0
0
0
0
0
0
EFTUI
0
VER0
Table 1. Control Register Map Summary
7.1 MEMORY ADDRESS POINTER (MAP)
7
INCR
6
MAP6
5
MAP5
4
MAP4
INCR - Auto Increment Address Control Bit
Default = ‘0’
0 - Disable
1 - Enable
MAP6:MAP0 - Register Address
3
MAP3
2
MAP2
1
MAP1
0
MAP0
Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8405A.
16
DS469PP4
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