CS8405A-CZ(2002) Просмотр технического описания (PDF) - Cirrus Logic

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CS8405A-CZ
(Rev.:2002)

96 kHz Digital Audio Interface Transmitter

Cirrus Logic 

CS8405A

mode operation. The CS8405A is set to mono

mode by the MMT control bit.

In mono mode, the input port will run at the audio

sample rate (Fs), while the AES3 transmitter frame

rate will be at Fs/2. Consecutive left or right chan-

nel serial audio data samples may be selected for

transmission on the A and B sub-frames, and the

channel status block transmitted is also selectable.

Using mono mode is only necessary if the incom-

ing audio sample rate is already at 96 kHz and con-

tains both left and right audio data words. The

“mono mode” AES3 output stream may also be

achieved by keeping the CS8405A in normal stereo

mode, and placing consecutive audio samples in

the left and right positions in an incoming 48 kHz

word rate data stream.

TCBL

In or Out

VLRCK

VCU

Input

Tth

Tsetup

Thold

VCU[0]

VCU[1]

VCU[2]

VCU[3]

VCU[4]

SDIN

Input

TXP(N)

Output

Data [4]

Z Data [0]

TCBL

Tth

In or Out

VLRCK

U

Input

Data [5]

Data [6]

Data [7]

Data [8]

Y Data [1]

X Data [2]

Y Data [3]

AES3 Transmitter in Stereo mode

X Data [4]

Tsetup => 7.5% AES3 frame time

Thold = 0

Tth > 3OMCK if TCBL is Input

U[0]

U[2]

SDIN

Input

TXP(N)

Output

Data [4]

Data [5]

Z

Data [0]*

* Assume MMTLR = 0

Data [6]

Data [7]

Y

Data [2]*

Data [8]

X

Data [4]*

TXP(N)

Output

Z

Data [1]*

* Assume MMTLR = 1

Y

Data [3]*

AES3 Transmitter in Mono mode

X

Data [5]*

Tsetup => 15% AES3 frame time

Thold = 0

Tth > 3OMCK if TCBL is Input

VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing.

VLRCK duty cycle is 50%.

In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate.

If the serial audio input port is on slave mode and TCBL is an output, then VLRCK=ILRCK if SILRPOL=0 and

VLRCK= ILRCK if SILRPOL =1.

If the serial audio input port is in master mode and TCBL is an input, then VLRCK=ILRCK if SILRPOL=0 and

VLRCK= ILRCK if SILRPOL =1.

Figure 7. AES3 Transmitter Timing for C, U, and V Pin Input Data

DS469PP4

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