SAA7187 Просмотр технического описания (PDF) - Philips Electronics
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SAA7187 Datasheet PDF : 36 Pages
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Philips Semiconductors
Digital video encoder (DENC2-SQ)
Preliminary specification
SAA7187
FUNCTIONAL DESCRIPTION
The digital video encoder (DENC2-SQ) encodes digital
luminance and chrominance into analog CVBS and
simultaneously S-Video (Y/C) signals. NTSC-M and PAL
B/G standards also sub-standards are supported.
The basic encoder function consists of subcarrier
generation and colour modulation also insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements RS-170-A and CCIR 624.
For ease of analog post filtering the signals are twice
oversampled with respect to pixel clock before
digital-to-analog conversion.
For total filter transfer characteristics see Figs 3 to 6 for
60 Hz field rate, and Figs 7 to 10 for 50 Hz field rate. The
DACs are realized with full 10-bit resolution. The encoder
provides three 8-bit wide data ports, that serve different
applications.
The VP1 port accepts 8 lines multiplexed Cb-Y-Cr data
(CCIR 656 mode), or Y data only (444 mode).
The VP2 port accepts Cr data in 444 input mode.
The VP3 port accepts Cb data (444 input mode) or
multiplexed Cb/Cr data (422 input mode). If not used for
video input data, it can alternatively also handle the data of
an 8-bit wide microprocessor interface.
Minimum suppression of output chrominance alias
components approximately 1 MHz due to high frequency
444 input is better than 12 dB.
The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656
(D1 format) compatible, but the SAV, EAV, etc. codes are
not decoded.
A crystal-stable master clock (LLC) of 24.54 or 29.5 MHz,
which is twice the line-locked pixel clock, needs to be
supplied externally. Optionally, a crystal oscillator
input/output pair of pins and an on-chip clock driver is
provided. Additionally, a DMSD2 compatible clock
interface, using CREF (input or output) and RTC (see
“data sheet SAA7191B” ) is available.
The DENC2-SQ synthesizes all necessary internal
signals, colour subcarrier frequency, and synchronization
signals, from that clock. DENC2-SQ can be timing master
or slave.
The IC also contains Closed Caption and Extended Data
Services Encoding (Line 21); it also supports OSD via
KEY and three-bit overlay techniques by a 24 × 8 LUT.
The IC can be programmed via I2C-bus or 8-bit MPU
interface, but only one interface configuration can be
active at a time; if 422 or 444 input format is being used,
only the I2C-bus interface can be selected.
A number of possibilities are provided for setting of
different video parameters such as:
Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the control interfaces to abort any running bus transfer and
to set register 3AH to contents 00H, register 61H to
contents 15H, and register 6CH to contents 00H. All other
control registers are not influenced by a reset.
Data manager
In the data manager, the demultiplexing scheme is chosen
in accordance with the input format.
Depending on hardware conditions (signals on pins KEY,
OSD2 to OSD0), and software programming either data
from the VP ports or from the OSD port are selected to be
encoded to CVBS and Y/C signals.
Optionally, the OSD colour look-up tables located in this
block, can be read out in a pre-defined sequence (8 steps
per active video line), achieving e.g. a colour bar test
pattern generator without need for an external data
source. The colour bar function is only under software
control.
Encoder
VIDEO PATH
The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y/C signals.
Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). After having been inserted a fixed
synchronization level, in accordance with standard
composite synchronization schemes, a variable blanking
level, programmable also in a certain range, is inserted.
Transients of both synchronization pulses and start/stop of
blanking are reduced compared to overall luminance
bandwidth.
1995 Sep 21
7
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