SAA4955TJ Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

Список матч

SAA4955TJ

2.9-Mbit field memory

Philips Electronics 

Philips Semiconductors

2.9-Mbit field memory

Product specification

SAA4955TJ

corresponds to decimal address 40. The highest block

address is 17FFH. This block has a decimal start address

of 245720 and an end address 245759.

If a read or write reset operation is not performed, the next

read or write pointer address after 245759 will be

address 0 due to pointer wraparound. Note that reset read

and reset write operations should occur in a single

sequence. If one pointer wraps around while the other is

reset, either 12 words will be lost or 12 words of undefined

data will be read.

DATA INPUTS: D0 TO D11 AND WRITE CLOCK: SWCK

A positive transition on the SWCK write clock latches the

data on inputs D0 to D11, provided WE was HIGH at the

previous positive transition of SWCK. The data input

set-up (tsu(D)) and hold (th(D)) times are referenced to the

positive transition of SWCK (see Fig.4). The latched data

will only be written into memory if IE was HIGH at the

previous positive transition of SWCK.

WRITE ENABLE: WE

Pin WE is used to enable or disable a data write operation.

The WE signal controls data inputs D0 to D11. In addition,

the internal write address pointer is incremented if WE is

HIGH at the positive transition of the SWCK write clock.

WE set-up (tsu(WE)) and hold (th(WE)) times are referenced

to the positive edge of SWCK (see Fig.7).

INPUT ENABLE: IE

Pin IE is used to enable or disable a data write operation

from the D0 to D11 data inputs into memory. The latched

data will only be written into memory if the IE and WE

signals were HIGH during the previous positive transition

of SWCK. A LOW level on IE will prevent the data being

written into memory and existing data will not be

overwritten (write mask function; see Fig.9). The IE set-up

(tsu(IE)) and hold (th(IE)) times are referenced to the positive

edge of SWCK (see Fig.8).

Read operation

Read operations are controlled by the SRCK, RSTR, RE

and OE signals. A read operation starts with a reset read

address pointer (RSTR) operation, followed by a

sequence of SRCK clock cycles during which time RE and

OE must be held HIGH. Read operations between two

successive reset read operations must contain at least

20 SRCK read clock cycles while RE is HIGH.

RESET READ: RSTR

The first positive transition of SRCK after RSTR goes from

LOW to HIGH resets the read address pointer to the lowest

address (−12 decimal; see Figs 10 and 11). If RE is LOW,

however, the reset read operation to the lowest address

will be delayed until the first positive transition of SRCK

after RE goes HIGH. RSTR set-up (tsu(RSTR)) and hold

(th(RSTR)) times are referenced to the rising edge of SRCK

(see Fig.10). The reset read operation may also be

asynchronously related to the SRCK signal if RE is LOW.

RSTR needs to stay LOW for a single SRCK cycle before

another reset read operation can take place.

RANDOM READ BLOCK ACCESS MODE

The SAA4955TJ will enter random read block access

mode if the following signal sequence is applied to control

inputs RE and OE during the first four SRCK read clock

cycles after a reset read (see Fig.12):

At the 1st and 2nd positive transitions of SRCK,

OE must be LOW and RE must be HIGH

At the 3rd and 4th positive transitions of SRCK,

OE must be HIGH and RE must be LOW.

During this time, control signals RE and OE will function as

defined for normal operation. The Most Significant Bit

(MSB) of the block read address is applied to the OE input

pin at the 5th positive transition of SRCK. The remaining

12 bits of the 13-bit read block address must be applied, in

turn, to OE at the following 12 positive transitions of SRCK.

The Least Significant Bit (LSB) of the block address is

applied at the 17th positive transition of SRCK. A read

latency period of 20 additional SRCK clock cycles is

required before read access to the new block address is

possible. During this period, data is transferred from the

memory array to the serial read and parallel read registers

and the read pointer is set to the new block address.

Block address values between 0 and 6143 are valid.

Values outside this range must be avoided because invalid

block addresses can result in abnormal operation or a

lock-up condition. Recovery from lock-up requires a

standard reset read operation.

The data output pins are not controlled by the OE pin and

are forced into high impedance mode from the 3rd to

the 17th positive transition of SRCK. OE should be held

LOW during the read latency period. RE must remain LOW

from the 3rd positive transition of SRCK to the 20th read

latency SRCK clock cycle.

After the 20th read latency SRCK clock cycle, RE and OE

may be switched HIGH to prepare for reading new data

1999 Apr 29

7

Share Link: