SAA4955TJ Просмотр технического описания (PDF) - Philips Electronics
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SAA4955TJ Datasheet PDF : 28 Pages
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Philips Semiconductors
2.9-Mbit field memory
Product specification
SAA4955TJ
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.(1)
MAX.
UNIT
Read cycle timing; note 3
tACC
access time after SRCK
see Fig.10
−
−
21
ns
ten(Q)
output enable time after SRCK see Fig.14
−
−
21
ns
tdis(Q)
output disable time after SRCK note 4; see Fig.14
−
−
12
ns
th(Q)
output hold time after SRCK
see Fig.10
3
−
−
ns
Tcy(SRCK) SRCK cycle time
see Fig.10
26
−
−
ns
tW(SRCKH) HIGH-level pulse width of SRCK see Fig.10
7
−
−
ns
tW(SRCKL) LOW-level pulse width of SRCK see Fig.10
7
−
−
ns
tsu(RSTR)
set-up time RSTR
see Fig.10
5
−
−
ns
th(RSTR)
hold time RSTR
see Fig.10
3
−
−
ns
tsu(RE)
set-up time RE
see Fig.13
5
−
−
ns
th(RE)
hold time RE
see Fig.13
3
−
−
ns
tW(REL)
LOW-level pulse width of RE see Fig.13
9
−
−
ns
tsu(OE)
set-up time OE
see Fig.14
5
−
−
ns
th(OE)
hold time OE
see Fig.14
3
−
−
ns
tW(OEL)
LOW-level pulse width of OE see Fig.14
9
−
−
ns
tt
transition time (rise and fall)
see Fig.10
−
3
30
ns
Notes
1. Typical values are valid for Tamb = 25 °C, VDD = VDD(O) = VDD(P) = 3.3 V, all voltages referenced to GND. See Fig.1
for configuration.
2. The write cycle timing set-up and hold times are related to VIL of the rising edge of SWCK. They are valid for the
specified LOW- and HIGH-level input voltages (VIL and VIH).
3. The read cycle timing set-up and hold times are related to VIL of the rising edge of SRCK. They are valid for the
specified LOW- and HIGH-level input voltages (VIL and VIH). The load on each output is a 30 pF capacitor to ground
in parallel with a 218 Ω resistor to 1.31 V.
4. Disable times specified are from the initiating edge until the output is no longer driven by the memory. Disable times
are measured by observing the output waveforms. Low values of load resistor and capacitor have to be used to
obtain a short time constant.
1999 Apr 29
11
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