SAA4955TJ Просмотр технического описания (PDF) - Philips Electronics
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SAA4955TJ Datasheet PDF : 28 Pages
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Philips Semiconductors
2.9-Mbit field memory
Product specification
SAA4955TJ
CHARACTERISTICS
VDD = VDD(O) = VDD(P) = 3.0 to 3.6 V; Tamb = 0 to 70 °C; 3 ns input transition times; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.(1)
MAX.
UNIT
Supply
VDD, VDD(O) supply voltages (pins 19 and 22)
3.0
3.3
VDD(P)
supply voltage (pins 20 and 21)
3.0
3.3
IDD(tot)
total supply current
minimum write/read
−
22
(IDD(tot) = IDD + IDD(O) + IDD(P))
cycle; outputs open
IDD
operating supply current
minimum write/read cycle −
20
IDDstd
stand-by supply current
after 1 RSTW/RSTR
−
3
cycle; WE, RE and
OE LOW
IDD(O)
supply current
minimum write/read
−
2
cycle; outputs open
IDD(P)
supply current
−
0
Inputs (pins 3 to 18 and 23 to 26)
VIH
HIGH-level input voltage
2.0
−
VIL
LOW-level input voltage
−0.5 −
ILI
input leakage current
VI = 0 V to VDD(P)
−10
−
Ci
input capacitance
f = 1 MHz; VI = 0 V
−
−
Outputs (pins 27 to 38)
VOH
HIGH-level output voltage
IOH = −5 mA
2.4
−
VOL
LOW-level output voltage
IOL = 4.2 mA
−
−
ILO
output leakage current
VO = 0 V to VDD(Q);
RE and OE LOW
−10
−
Co
output capacitance
f = 1 MHz; VO = 0 V
−
−
Write cycle timing; note 2
Tcy(SWCK)
tW(SWCKH)
tW(SWCKL)
tsu(D)
SWCK cycle time
SWCK HIGH pulse width
SWCK LOW pulse width
set-up time data inputs
(D0 to D11)
see Fig.3
see Fig.3
see Fig.3
see Fig.3
26
−
7
−
7
−
5
−
th(D)
tsu(RSTW)
th(RSTW)
tsu(WE)
th(WE)
tW(WEL)
tsu(IE)
th(IE)
tW(IEL)
tt
hold time data inputs (D0 to D11) see Fig.3
set-up time RSTW
see Fig.3
hold time RSTW
see Fig.3
set-up time WE
see Fig.7
hold time WE
see Fig.7
WE LOW pulse width
see Fig.7
set-up time IE
see Fig.8
hold time IE
see Fig.8
IE LOW pulse width
see Fig.8
transition time (rise and fall)
see Fig.3
3
−
5
−
3
−
5
−
3
−
8
−
5
−
3
−
8
−
−
3
3.6
V
5.5
V
70
mA
60
mA
10
mA
10
mA
1
mA
VDD(P) + 0.3 V
+0.8
V
+10
µA
7
pF
−
V
0.4
V
+10
µA
10
pF
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
ns
30
ns
1999 Apr 29
10
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