RF2968 Просмотр технического описания (PDF) - RF Micro Devices

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RF2968

BLUETOOTH™ TRANSCEIVER

RF Micro Devices 

RF2968

Preliminary

11

State

OFF

PWRON WAIT XTL

HOLD XTL

IDLE

SLEEP

WAIT XTL

WAIT DATA SYNC

DATA SYNC

ENABLE PA

TX DATA

DISABLE PA

RX PLL WAIT

RX DATA

Description

All circuits are powered down and reset; configuration data is lost. (CLRB=0)

Reset is released (CLRB=1) and the oscillator is turned on (PDXTAL=1).

This mode is entered when the oscillator has settled. Configuration data can be read through the DBus inter-

face.

This is a standby mode. Data can be read into the control registers (through the DBus) and the oscillator

remains on. All other circuits are powered down.

The device normally enters this mode from IDLE, in which case every circuit is powered down but not reset, so

that configuration data is retained. The device may also enter this mode from any other except PWRON WAIT

XTL or HOLD XTL, but the TXEN and RXEN functions are not overridden, so that TX and RX circuits may

remain on.

The oscillator is turned on (PDXTAL=1) and allowed to settle before returning to IDLE mode.

This is the start of the transmit sequence. This mode is entered by the baseband writing to the control registers

(through the DBus). When this happens, TXEN goes high, turning on the synthesizer and initializing a fixed

delay, after which all the transmit circuits (except for the PA) are turned on (PD_TX=1). The baseband waits

175µs before it starts sending transmit data to the RF2968 (to allow the synthesizer to settle). The device can-

not be in both transmit and receive modes at the same time, so RXEN must be low to enter this mode.

A transition on BDATA1 (0 to 1) starts the synchronization of data between the RF2968 and the baseband

device.

The PA is powered up (PDPA=1) and ready to begin transmitting.

Data is transmitted in this mode. (The synthesizer has settled and the data path synchronized.)

The PA is powered down (PDPA=0). 1µs later, the synthesizer and the rest of the transmit circuits are powered

down (PD_TX=0). This delay prevents any “unwanted transmission” during power down. The device then

returns to IDLE mode when the baseband writes to the control registers and drives TXEN low.

This is the start of the receive sequence and is entered from IDLE mode when a control register write from the

baseband forces RXEN high. This turns on the synthesizer and starts a timer which powers up the receive path

circuits after a fixed delay (PD_RX=1). The baseband device expects to receive data 175µs after the control

register write.

Received data is sent to the baseband device via BDATA1 (unsynchronized) and RECDATA (synchronized with

RECCLK). Within this state, there are two DC estimation modes. In the “access code” mode, the RF2968 uses

a fast DC estimation to adjust for large frequency offsets. An internal timer (or alternatively BPKTCTL) signals

the end of the sync word, placing the DC estimation circuitry in the “payload” mode, in which compensation is

made for small frequency offsets. A control register write from the baseband drives RXEN low and returns the

device to IDLE mode. This turns off the receive path (PD_RX=0) and the synthesizer.

11-134

Rev A13 010912

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