QT300 Просмотр технического описания (PDF) - Quantum Research Group

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QT300

CAPACITANCE TO DIGITAL CONVERTER

Quantum Research Group 

If SM is set for idle-low SCK: Data is shifted out

of the QT300 on the rising edge of SCK and should

be shifted into the host on the falling edge of SCK.

If SM is set for idle-high SCK: Data is shifted out

of the QT300 on the falling edge of SCK and

should be shifted into the host on the rising edge of

SCK.

The maximum clock speed is 40kHz, and the

timings should obey the parameters Tskh and Tskl

in Table 7-2.

/DRDY - Data Ready (Optional); active low output

only. This indicates to the host that the device is

ready to send data back to the host. During idle

times this pin floats and therefore must be

connected to a pullup resistor.

The DRDY line can be used as a Slave Select line

(SS). The host does not need this line to operate in

many cases. DRDY can be used to 'frame' byte

transmissions.

Between bytes /DRDY will go high for a period

determined by the MLS setup parameter; the

minimum period is 8.3µs.

A typical Master mode SPI sequence is:

Figure 4-1 UART and Trigger Pulse Signal.

1) Host pulses /REQ low for ≥30µs.

2) QT300 acquires a signal in response to /REQ.

3) QT300 pulls /DRDY low when ready to send data.

4) Host detects /DRDY low and prepares to receive

data.

5) QT300 clocks out first byte of data (MSB).

6) QT300 sets /DRDY high for a duration determined

by Setup parameter MLS.

7) QT300 pulls /DRDY low.

8) QT300 clocks out the low byte (LSB).

9) QT300 releases /DRDY to float high.

overrun. The default value is 148 (resulting in a 500µs gap).

The relationship is:

Tmls (in µs) = (10 + MLS x 4) / 1.2

Where MLS = 0..255 (from user setup MLS)

Master SPI mode requires at least 3 signals to operate:

/REQ - Request Acquisition Input; Active low input-only.

When /REQ is pulled low, the QT300 wakes and starts an

acquire. The IC will transmit the resulting data only when

the acquire has finished.

/REQ must return high before the end of the burst. If

/REQ is still low at the end of the burst the part goes into

Setup mode. The minimum duration of /REQ is 30µs.

SDO - Serial Data Output; Idle low output-only. This is the

data output to the host during an SPI transfer. When not in

use, this pin floats. This pin should be connected to the

SDI input pin of the host device.

SCK - SPI clock; Idle high or idle low, output-only. The idle

state is determined in Setups by the serial mode (SM)

parameter.

4 Serial 1W UART Interface

The single wire ('1W') UART interface allows all

communications to take place over a single bidirectional line

with a 10K pullup resistor. The host device triggers the

QT300 to acquire by means of a pulse sent to the QT300

over the wire. The Baud rate is established by the width of

this pulse; the pulse width establishes the bit rate of the

UART transmission to follow. The QT300 then acquires, and

responds by sending two bytes of data back over the 1W line

with a delay between the bytes as determined by parameter

MLS.

1W operation permits a device to be controlled from a single

pin on a host controller, using either a hardware or software

UART. Several QT300’s can coexist on a single host pin,

provided there is some logic steering.

This mode is set via the cloning process using parameter SM

(see Section 6).

LQ

5

QT300 R1.02/0204

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