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PHB108NQ03LT Datasheet PDF : 14 Pages
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Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2: Ordering information
Type number
Package
Name
Description
Version
PHB108NQ03LT D2PAK
plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404
PHD108NQ03LT DPAK
plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT428
PHU108NQ03LT IPAK
plastic single-ended package; 3 leads (in-line)
SOT533
4. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
VDGR
VGS
ID
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage
drain current (DC)
IDM
peak drain current
Ptot
total power dissipation
Tstg
storage temperature
Tj
junction temperature
Source-drain diode
25 °C ≤ Tj ≤ 175 °C
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
Tmb = 100 °C; VGS = 5 V; Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tmb = 25 °C; Figure 1
IS
source (diode forward) current (DC) Tmb = 25 °C
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 43 A;
tp = 0.25 ms; VDD ≤ 25 V; RGS = 50 Ω;
VGS = 10 V; starting at Tj = 25 °C
Min
Max Unit
-
25
V
-
25
V
-
±20
V
-
75
A
-
75
A
-
240
A
-
187
W
−55
+175 °C
−55
+175 °C
-
75
A
-
240
A
-
180
mJ
9397 750 14707
Product data sheet
Rev. 03 — 18 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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