PDI1394P25BY Просмотр технического описания (PDF) - Philips Electronics
Номер в каталоге
Компоненты Описание
Список матч
PDI1394P25BY Datasheet PDF : 42 Pages
| |||
Philips Semiconductors
1-port 400 Mbps physical layer interface
Product data
PDI1394P25BY
TPBIAS connect-detect monitor IO used in suspend/resume
signaling and cable connection detection. For additional details of
suspend/resume operation, refer to the 1394a specification. The use
of suspend/resume is recommended for new designs.
The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the RESET input terminal is asserted low), when no active
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.
The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC is used in conjunction with the LCtrl bit (see Table 1
and Table 2) to indicate the active/power status of the LLC. The LPS
signal is also used to reset, disable, and initialize the PHY-LLC
interface (the state of the PHY-LCC interface is controlled solely by
the LPS input regardless of the state of the LCtrl bit).
The LPS input is considered inactive if it remains low for more than
2.6 µs and is considered active otherwise. When the PDI1394P25
detects that LPS is inactive, it will place the PHY-LLC interface into a
low-power reset state in which the CTL and D outputs are held in the
logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for
more than 26 µs, the PHY-LLC interface is put into a low-power
disabled state in which the SYSCLK output is also held inactive. The
PHY-LLC interface is also held in the disabled state during hardware
reset. The PDI1394P25 will continue the necessary repeater
functions required for normal network operation regardless of the
state of the PHY-LLC interface. When the interface is in the reset or
disabled state and LPS is again observed active, the PHY will
initialize the interface and return it to normal operation.
The PHY uses the C/LKON terminal to notify the LLC to power up
and become active. When activated, the C/LKON signal is a square
wave of approximately 163 ns period. The PHY activates the
C/LKON output when the LLC is inactive and a wake-up event
occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrI bit is cleared to 0. A
wake-up event occurs when a link-on PHY packet addressed to this
node is received, or conditionally when a PHY interrupt occurs. The
PHY de-asserts the C/LKON output when the LLC becomes active
(both LPS active and the LCtrl bit set to 1). The PHY also de-asserts
the C/LKON output when a bus-reset occurs unless a PHY interrupt
condition exists which would otherwise cause C/LKON to be active.
8.0 ABSOLUTE MAXIMUM RATINGS 1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITION
LIMITS
MIN
MAX
UNIT
VDD
VI
VI–5 V
VO
DC supply voltage
DC input voltage
5 volt tolerant input voltage range
DC output voltage range at any output
Electrostatic discharge
Human Body Model
Machine Model
–0.5
4.0
V
–0.5
VDD+0.5
V
–0.5
5.5
V
–0.5
—
VDD+0.5
V
2
kV
—
200
V
Tamb Operating free-air temperature range
0
+70
°C
Tstg
Storage temperature range
–65
+150
°C
NOTE:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2002 Oct 11
8
Share Link: 