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PDI1394P25BY

1-port 400 Mbps physical layer interface

Philips Electronics 

Philips Semiconductors

1-port 400 Mbps physical layer interface

Product data

PDI1394P25BY

Name

TPBIAS0

XI

XO

Pin Type

Cable

Crystal

LQFP

I/O

Pin

Numbers

Description

31

I/O Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper

operation of the twisted-pair cable drivers and receivers, and for signaling to the remote

nodes that there is an active cable connection. These terminals must be decoupled with a

0.3 µF–1 µF capacitor to ground.

42

— Crystal oscillator inputs. These terminals connect to a 24.576 MHz parallel resonant

43

fundamental mode crystal. The optimum values for the external shunt capacitors are

dependent on the specifications of the crystal used. Can also be driven by an external

clock generator (leave XO unconnected in this case and start supplying the external clock

before resetting the PDI1394P25). For more information, refer to Section 17.5

6.0 BLOCK DIAGRAM

LPS

/ISO

C/LKON

SYSCLK

LREQ

CTL0

CTL1

D0

D1

D2

D3

D4

D5

D6

D7

PC0

PC1

PC2

LINK

INTERFACE

I/O

RECEIVED DATA

DECODER/

RETIMER

ARBITRATION

AND CONTROL

STATE MACHINE

LOGIC

CABLE POWER

DETECTOR

CPS

CABLE PORT 0

TPA0+

TPA0–

TPB0+

TPB0–

R0

R1

TPBIAS0

PD

/RESET

BIAS VOLTAGE

AND

CURRENT

GENERATOR

TRANSMIT

DATA

ENCODER

CRYSTAL

OSCILLATOR,

XI

PLL SYSTEM,

AND CLOCK

XO

GENERATOR

SV01921

2002 Oct 11

6

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