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PCD4440T

Analog voice scrambler/descrambler

Philips Electronics 

Philips Semiconductors

Analog voice scrambler/descrambler

Product specification

PCD4440T

7.5 Serial clock input (SCL), Serial data input

(SDA)

SCL and SDA are serial clock and data lines which

conform to the I2C-bus specification. Both inputs must be

pulled up externally to VDD through resistors of

approximately 10 kΩ.

7.7 I2C-bus data configuration

The PCD4440T is always a slave receiver in the I2C-bus

configuration (the R/W bit = 0). The slave address consists

of 7 bits, where the least significant is set by the input on

A0. The more significant bits are fixed internally, as shown

in Fig.5. For definition of D0-D4, see Table 1.

7.6 Address input (A0)

A0 is the slave address input and is used to set one bit of

the slave address, so as to identify one of two PCD4440T

devices connected to the same I2C-bus. Whether another

PCD4440T is connected to the bus or not, A0 must be

connected to VDD or VSS. The remaining bits of the slave

address are fixed internally.

7.8 Signal input (IN), Signal output (OUT)

Signal input for the scrambler/descrambler is coupled into

a ‘Sallen and Key’ anti-aliasing filter configuration. A DC

bias voltage of 1⁄2VDD is built-in.

The analog signal output is buffered to achieve a relatively

low output impedance of roughly 1 kΩ which is sufficient to

drive the earpiece amplifier or similar applications.

handbook, full pagewidth

acknowledge

acknowledge

MSB

R/W

S 1 1 0 1 1 1 A0 0 A 0 0 0 0 D3 D2 D1 D0 A P

MGG732

slave address

data

internal STROBE

Fig.5 I2C-bus data format.

1996 Dec 20

8

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