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NJ88C25

FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)

Zarlink Semiconductor Inc 

NJ88C25 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNNJS88C25

DS3280-1.3

NJ88C25

FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)

The NJ88C25 is a synthesiser circuit fabricated on the GPS

CMOS process and is capable of achieving high sideband

attenuation and low noise performance. It contains a reference

oscillator, 11-bit programmable reference divider, digital and

sample-and-hold comparators, 10-bit programmable ‘M’ counter,

7-bit programmable ‘A’ counter, latched and buffered Band 0 and

Band 1 outputs and the necessary control and latch circuitry for

accepting and latching the input data.

Data is presented serially under external control from a suitable

microprocessor. Although 30 bits of data are initially required to

program all counters, subsequent updating can be abbreviated to

19 bits, when only the ‘A’, ‘M’ and ‘B’ counters require changing.

The NJ88C25 is intended to be used in conjunction with a two-

modulus prescaler such as the SP8710 series to produce a

universal binary coded synthesiser.

FEATURES

s Low Power Consumption

s High Performance Sample and Hold Phase Detector

s Serial Input with Fast Update Feature

ORDERING INFORMATION

NJ88C25 KA DG Ceramic DIL Package

NJ88C25 KA DP Plastic DIL Package

NJ88C25 KA MP Miniature Plastic DIL Package

PDA 1

18 CH

PDB 2

17 RB

FV 3

LD 4

16 MC

15 CAP

FIN

VSS

VDD

BAND 0

OSC IN

5 NJ88C25 14

6

13

7

12

8

11

9

10

ENABLE

CLOCK

DATA

BAND 1

OSC OUT

DG18, DP18, MP18

Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS

Supply voltage, VDD2VSS:

Input voltage

20·5V to 7V

Open drain output, pins 3 and 4:

7V

All other pins:

Storage temperature:

VSS20·3V to VDD10·3V

265°C to 1150°C (DG package)

255°C to 1125°C

(DP and MP packages)

RB CAP CH

17 15 18

9

OSC IN

10

OSC OUT

12

DATA 14

ENABLE

13

CLOCK

8

BAND 0

11

BAND 1

5

FIN

7

VDD

6

VSS

REFERENCE COUNTER

(11BITS)

LATCH 6 LATCH 7 LATCH 8

‘R’ REGISTER

‘B’ REGISTER

‘M’ REGISTER

LATCH 6 LATCH 1 LATCH 2 LATCH 3

‘M’ COUNTER

(10 BITS)

42

fr

fV

‘A’ REGISTER

LATCH 4 LATCH 5

‘A’ COUNTER

(7 BITS)

CONTROL LOGIC

SAMPLE/HOLD

PHASE

DETECTOR

1 PDA

FREQUENCY/

PHASE

DETECTOR

2 PDB

4 LOCK DETECT (LD)

VSS

3 FV

VSS

16

MODULUS

CONTROL

OUTPUT (MC)

Fig.2 Block diagram

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