AD6622 Просмотр технического описания (PDF) - Analog Devices

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AD6622

Four-Channel, 75 MSPS Digital Transmit Signal Processor (TSP)

Analog Devices 

AD6622

DS (RD)

R/W (WR)

tHDS

tHRW

CS

A[2:0]

D[7:0]

DTACK

(RDY)

tSAM

tHAM

VALID ADDRESS

tSAM

tHAM

VALID DATA

tACC

tDDTACK

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK.

2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1

3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER

VERSUS A RAM REGISTER.

4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.

Figure 7. MNM Microport Write Timing Requirements

DS (RD)

R/W (WR)

tHDS

CS

A[2:0]

D[7:0]

DTACK

(RDY)

tSAM

tZD

tACC

VALID ADDRESS

tDD

tHA

tZD

VALID DATA

tDDTACK

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF DS TO THE FE OF DTACK.

2. tACCFAST REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 3, 2, 1

3. tACCMEDIUM REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 4, 5, AND 0 IF THE ACCESS IS TO A CONTROL REGISTER

VERSUS A RAM REGISTER.

4. tACCSLOW REQUIRES A MAXIMUM OF SIX CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.

Figure 8. MNM Microport Read Timing Requirements

–6–

REV. 0

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