AD6622 Просмотр технического описания (PDF) - Analog Devices
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AD6622 Datasheet PDF : 28 Pages
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AD6622
Name
Parameter (Conditions)
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
MODE MNM Write Timing:
tHDS
DS(RD) to DTACK(RDY) Hold Time
tHRW
tSAM
R/W(WR) to DTACK(RDY) Hold Time
Address/Data to R/W(WR) Setup Time
tHAM
Address/Data to R/W(WR) Hold Time
tDDTACK
tACCFAST
DS(RD) to DTACK(RDY) Delay
R/W(WR) to DTACK(RDY) Low Delay
tACCMEDIUM R/W(WR) to DTACK(RDY) Low Delay
tACCSLOW
R/W(WR) to DTACK(RDY) Low Delay
MODE MNM Read Timing:
tSAM
Address to DS(RD) Setup Time
tHA
Address to Data Hold Time
tZD
tDD
tDDTACK
tACCFAST
tACCMEDIUM
tACCSLOW
Data Three-State Delay
DTACK(RDY) to Data Delay
DS(RD) to DTACK(RDY) Delay
DS(RD) to DTACK(RDY) Low Delay
DS(RD) to DTACK(RDY) Low Delay
DS(RD) to DTACK(RDY) Low Delay
NOTES
1All Timing Specifications valid over VDD range of 2.4 V to 3.3 V.
Specifications subject to change without notice.
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level Min
AD6622AS
Typ Max
Unit
IV
0
IV
0
IV
0
IV
0
IV
IV
2 × tCLK
IV
3 × tCLK
IV
4 × tCLK
IV
0
IV
0
IV
0
IV
IV
IV
2 × tCLK
IV
3 × tCLK
IV
4 × tCLK
ns
ns
ns
ns
1 × tCLK
ns
3 × tCLK
ns
4 × tCLK
ns
5 × tCLK
ns
ns
ns
ns
tCLK – 10 ns
1 × tCLK
ns
3 × tCLK
ns
4 × tCLK
ns
5 × tCLK
ns
CLK
tCLK
tCLKL
tCLKH
tSO
OUT[17:0],
QOUT
tHO
tZO
tZO
OEN
Figure 1. Parallel Output Switching Characteristics
CLK
SCLK
SDFS
SDI
tDSCLK
tDSDFS
tDSDFS
CLKn
tSSI
tHSI
DATAn
Figure 2. Serial Port Switching Characteristics
CLK
tSI
tHI
IN[17:0],
QIN
Figure 3. Wideband Input Timing
CLK
SYNC
tSS
tHS
Figure 4. SYNC Timing Inputs
–4–
REV. 0
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