MT8960AE Просмотр технического описания (PDF) - Mitel Networks

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MT8960AE

Integrated PCM Filter Codec

Mitel Networks 

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

Receive (D/A) Path (cont’d)

Characteristics

Sym Min Typ* Max Units

Test Conditions

11 Envelope Delay

DAR

12

Envelope Delay 1000-2600 Hz DDR

Variation with 600-3000 Hz

Frequency

400-3200 Hz

210

90

170

265

µs @ 1004 Hz

µs Input Signal:

µs 400 - 3200 Hz digital

µs sinewave at 0 dBm0

13 Gain Relative to <200 Hz

Gain @ 1004 Hz 200 Hz

A (See Figure 11) 300-3000 Hz

N

3300 Hz

A

3400 Hz

L

4000 Hz

O

≥4600 Hz

G

14 Crosstalk A/D to D/A

GRR

CTTR

-0.5

-0.125

-0.350

-0.80

0.125 dB 0 dBm0 Input Signal

0.125 dB

0.125 dB Receive

0.030 dB Filter

-0.100 dB Response

-14.0 dB

-28.0 dB

-70 dB 0 dBm0 @ 1.02 kHz

in A/D

15 Power Supply

Rejection

VDD

PSRR3 33

VEE

PSRR4 35

dB Input 50 mVRMS at

dB 1.02 kHz

16 Overload Distortion

(See Fig. 15)

Input frequency=1.02 kHz

* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.

Note 7: 0dBm0=1.185 VRMS for µ-Law codec and 0dBm0=1.231 VRMS for A-Law codec.

125 µs

C2i

INPUT

F1i

INTERNAL

ENABLE

AAAAAA

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

AAAAAAAAAAAA

AAAAAAAAAA

DSTo

OUTPUT

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

7

6

5

4

3

2

1

0 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

HIGH IMPEDANCE

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 7

DSTi

INPUT

5V

CA

(Mode 3)

0V

76543210

76

CSTi

INPUT

LOAD

A-REGISTER

LOAD

B-REGISTER

6-34

76543210

76543210

Figure 9a - Timing Diagram - 125µs Frame Period

76

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