HM5257165BTD-75 Просмотр технического описания (PDF) - Elpida Memory, Inc

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HM5257165BTD-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5257165B/HM5257805B/HM5257405B-75/A6

Pin Arrangement (HM5257805B)

VCC

DQ0

VCCQ

NC

DQ1

VSSQ

NC

DQ2

VCCQ

NC

DQ3

VSSQ

NC

VCC

NC

WE

CAS

RAS

CS

BA0

BA1

A10

A0

A1

A2

A3

VCC

54-pin TSOP

1

54

2

53

3

52

4

51

5

50

6

49

7

48

8

47

9

46

10

45

11

44

12

43

13

42

14

41

15

40

16

39

17

38

18

37

19

36

20

35

21

34

22

33

23

32

24

31

25

30

26

29

27

28

(Top view)

VSS

DQ7

VSSQ

NC

DQ6

VCCQ

NC

DQ5

VSSQ

NC

DQ4

VCCQ

NC

VSS

NC

DQM

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

VSS

Pin Description

Pin name

A0 to A12,

BA0, BA1

DQ0 to DQ7

CS

RAS

CAS

Function

Address input

Pin name

WE

 Row address

A0 to A12

DQM

 Column address A0 to A9, A11 CLK

 Bank select address BA0/BA1 (BS) CKE

Data-input/output

Chip select

Row address strobe command

Column address strobe command

VCC

VSS

VCCQ

VSSQ

NC

Function

Write enable

Input/output mask

Clock input

Clock enable

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

Data Sheet E0081H10

4

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