HM5257165BTD-75 Просмотр технического описания (PDF) - Elpida Memory, Inc

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HM5257165BTD-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5257165B/HM5257805B/HM5257405B-75/A6

Pin Arrangement (HM5257165B)

VCC

DQ0

VCCQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VCCQ

DQ5

DQ6

VSSQ

DQ7

VCC

DQML

WE

CAS

RAS

CS

BA0

BA1

A10

A0

A1

A2

A3

VCC

54-pin TSOP

1

54

2

53

3

52

4

51

5

50

6

49

7

48

8

47

9

46

10

45

11

44

12

43

13

42

14

41

15

40

16

39

17

38

18

37

19

36

20

35

21

34

22

33

23

32

24

31

25

30

26

29

27

28

(Top view)

VSS

DQ15

VSSQ

DQ14

DQ13

VCCQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VCCQ

DQ8

VSS

NC

DQMU

CLK

CKE

A12

A11

A9

A8

A7

A6

A5

A4

VSS

Pin Description

Pin name

Function

Pin name

Function

A0 to A12,

BA0, BA1

Address input

WE

Write enable

 Row address

A0 to A12

DQMU/DQML Input/output mask

 Column address A0 to A9

CLK

Clock input

 Bank select address BA0/BA1 (BS) CKE

Clock enable

DQ0 to DQ15

CS

RAS

CAS

Data-input/output

Chip select

Row address strobe command

Column address strobe command

VCC

VSS

VCCQ

VSSQ

NC

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

Data Sheet E0081H10

3

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