HM5257165BTD-75 Просмотр технического описания (PDF) - Elpida Memory, Inc

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HM5257165BTD-75

512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5257165B/HM5257805B/HM5257405B-75/A6

From READ with AUTO-PRECHARGE state, command operation

To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and

the SDRAM then enters precharge mode.

To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)

Attempting to make the currently active bank active results in an illegal command.

From WRITE state, command operation

To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.

To [READ], [READ A]: These commands stop a burst and start a read cycle.

To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.

To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.

From WRITE with AUTO-PRECHARGE state, command operation

To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the

synchronous DRAM enters precharge mode.

To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)

Attempting to make the currently active bank active results in an illegal command.

From REFRESH state, command operation

To [DESL], [NOP]: After an auto-refresh cycle (after tRC), the SDRAM automatically enters the IDLE state.

Data Sheet E0081H10

18

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