PDM4M4110 Просмотр технического описания (PDF) - Paradigm Technology

Номер в каталоге

Компоненты Описание

Список матч

PDM4M4110

512K x 32 CMOS Static RAM Module

Paradigm Technology 

PRELIMINARY

Timing Waveforms of Write Cycle No.1(1)

tWC

ADDRESS

OE

CS

tWR

tAW

tAS

tWP(2)

WE

PDM4M4110

DOUT

tOHZ(4,9)

tWHZ(6)

tDW

tDH

DIN

Timing Waveforms of Write Cycle No.2(1,6)

tWC

ADDRESS

CS

tAW

tCW

(5)

tWP(2)

tWR(3)

WE

tAS

DOUT

tWHZ(4,9)

tOH

tOW(9)

(7)

tDW

tDH

(8)

DIN

NOTES 1 WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap (tWP) of a LOW CS .

3. tWR is measured from the earlier of CS or WE going HIGH to end the write cycle.

4. During this period, I/O pins are in the output state, and input signals to the opposite phase to the outputs must not

be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-

impedance state.

6. OE is continuously LOW (OE = VIL)

7. DOUT is the same phase of write data of this write cycle.

8. If CS is LOW during this period, I/O pins are in the output state. Then the data input signals of the opposite phase

to the outputs must not be applied to them.

9. Transition is measured ±200 mV for steady state with a 5 pF load (including scope and jig). This parameter is deter-

mined by device characteristics but is not production tested.

8-72

Rev 2.3 - 1/15/96

Share Link: