LH51BV1000JY-70LL Просмотр технического описания (PDF) - Sharp Electronics
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LH51BV1000JY-70LL Datasheet PDF : 11 Pages
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LH51BV1000J
CMOS 1M (128K × 8) Static RAM
READ CYCLE (TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V)
PARAMETER
SYMBOL MIN.
MAX.
Read cycle time
tRC
70
Address access time
tAA
70
CE1 access time
tACE1
70
CE2 access time
tACE2
70
Output enable to output valid
tOE
40
Output hold from address change
tOH
10
CE1 Low to output active
tLZ1
5
CE2 High to output active
tLZ2
5
OE Low to output active
tOLZ
0
CE1 High to output in High impedance
tHZ1
30
CE2 Low to output in High impedance
tHZ2
30
OE High to output in High impedance
tOHZ
30
NOTE:
1. Active output to High impedance to output active tests specified for a
±200 mV transition from steady state levels into the test load.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE (TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V)
PARAMETER
SYMBOL MIN.
MAX.
UNIT
Write cycle time
tWC
70
ns
Chip enable to end of write
tCW
60
ns
Address valid to end of write
tAW
60
ns
Address setup time
tAS
0
ns
Write pulse width
tWP
55
ns
Write recovery time
tWR
0
ns
Input data setup time
tDW
30
ns
Input data hold time
tDH
0
ns
WE High to output active
tOW
5
ns
WE Low to output in High impedance
tWZ
30
ns
OE High to output in High impedance
tOHZ
30
ns
NOTE:
1. Active output to High impedance to output active tests specified for a
±200 mV transition from steady state levels into the test load.
NOTE
1
1
1
1
1
1
NOTE
1
1
1
4
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