KSZ8841-16 Просмотр технического описания (PDF) - Micrel
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KSZ8841-16 Datasheet PDF : 105 Pages
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Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Ball Description for KSZ8841-16 Chip (8/16-Bit)
Ball Number Ball Name
E8
TEST_EN
D10
SCAN_EN
A10
P1LED2
B10
P1LED1
C10
P1LED0
Type
I
I
Opu
Opu
Opu
Ball Function
Test Enable
For normal operation, pull-down this ball to ground.
Scan Test Scan Mux Enable
For normal operation, pull-down this ball to ground.
Port 1 LED indicators1 defined as follows:
Switch Global Control Register 5:
SGCR5 bit [15,9]
P1LED32
[0,0] Default
[0,1]
—
—
P1LED2
Link/Act
100Link/Act
P1LED1
Full duplex/Col 10Link/Act
P1LED0
Speed
Full duplex
Reg. SGCR5 bit [15,9]
P1LED32
[1,0]
[1,1]
Act
—
P1LED2
Link
—
P1LED1
Full duplex/Col —
P1LED0
Speed
—
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is ball A4.
D9
RDYRTNN
Ipd
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous read
cycles. If the host doesn’t connect to this ball, assert this ball.
A8
BCLK
Ipd
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This ball should be tied Low or unconnected if it is in asynchronous mode.
D8
PMEN
Opu Power Management Event Not
When asserted (Low), this signal indicates that a power management event has
occurred in the system when a wake-up signal is detected by KSZ8841M.
B8
SRDYN
Opu Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-
like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal
is synchronous to the bus clock signal BCLK.
C8
INTRN
Opd Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this ball
need an external 4.7K pull-up resistor.
A7
LDEVN
Opd Local Device Not
October 2007
17
M9999-102207-1.6
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