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KSZ8841-16

Single-Port Ethernet MAC Controller with Non-PCI Interface

Micrel 

Micrel, Inc.

KSZ8841-16/32 MQL/MVL/MBL

Pin Description for KSZ8841-16 Chip (8/16-Bit)

Pin Number Pin Name

1

TEST_EN

Type

I

2

SCAN_EN I

3

P1LED2

Opu

4

P1LED1

Opu

Pin Function

Test Enable

For normal operation, pull-down this pin-to-ground.

Scan Test Scan Mux Enable

For normal operation, pull-down this pin-to-ground.

Port 1 LED indicators1 defined as follows:

Chip Global Control Register: CGCR

bit [15,9]

P1LED32

[0,0] Default

[0,1]

—

—

P1LED2

Link/Act

100Link/Act

P1LED1

Full duplex/Col 10Link/Act

P1LED0

Speed

Full duplex

Reg. CGCR bit [15,9]

P1LED32

[1,0]

[1,1]

Act

—

P1LED2

Link

—

P1LED1

5

P1LED0

Opu

P1LED0

Full duplex/Col —

Speed

—

Notes:

1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;

Full Duplex = On (Full duplex); Off (Half duplex)

Speed = On (100BASE-T); Off (10BASE-T)

2. P1LED3 is pin 27.

6

NC

Opu

No Connect.

7

NC

Opu

No Connect.

8

NC

Opu

No Connect.

9

DGND

Gnd

Digital ground

10

VDDIO

P

3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

11

RDYRTNN Ipd

Ready Return Not:

For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If the

host doesn’t connect to this pin, assert this pin.

For burst mode (32-bit interface only): Host drives this pin low to signal waiting states.

12

BCLK

Ipd

Bus Interface Clock

Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.

This pin should be tied Low or unconnected if it is in asynchronous mode.

13

NC

Ipu

No Connect.

14

PMEN

Opu

Power Management Event Not

When asserted (Low), this signal indicates that a power management event has occurred

in the system when a wake-up signal is detected by KSZ8841M.

October 2007

12

M9999-102207-1.6

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