KL5BUDV003 Просмотр технического описания (PDF) - Unspecified
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KL5BUDV003 Datasheet PDF : 6 Pages
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KL5BUDV003
USB2.0 to PCI BUS
Pin #
I/O
Pin Name
Description
QFP
48
I/O
AD[26]
PCI address data bus
49
I/O
AD[25]
PCI address data bus
50
I/O
AD[24]
PCI address data bus
51
--
VDD
3.3V power pin
52
--
GND
Ground
53
--
VDD
3.3V power pin
54
--
GND
Ground
55
--
VDD18
1.8V power pin
56
--
GND
Ground
57
I/O
CBEN[3] Bus command byte enable signal
58
I
IDSEL
Device-select signal during configuration
59
I/O
AD[23]
PCI address data bus
60
--
GND
Ground
61
I/O
AD[22]
PCI address data bus
62
I/O
AD[21]
PCI address data bus
63
I/O
AD[20]
PCI address data bus
64
--
VDD18
1.8V power pin
65
--
GND
Ground
66
--
VDD
3.3V power pin
67
--
GND
Ground
68
I/O
AD[19]
PCI address data bus
69
I/O
AD[18]
PCI address data bus
70
--
GND
Ground
71
I/O
AD[17]
PCI address data bus
72
I/O
AD[16]
PCI address data bus
73
--
VDD
3.3V power pin
74
--
GND
Ground
75
I/O
CBEN[2] Bus command byte enable signal
76
I/O
FRAMEN Cycle-frame signal
77
--
GND
Ground
78
I/O
IRDYN
Initiator RDY signal
79
I/O
TRDYN
Target RDY signal
80
--
VDD18
1.8V power pin
81
--
GND
Ground
82
I/O
DEVSELN Device-select signal
83
--
VDD
3.3V power pin
84
--
GND
Ground
85
I/O
STOPN
Target termination signal
86
I/O
PAR
Even parity flag
87
--
GND
3.3V power pin
88
I/O
CBEN[1] Bus command byte enable signal
89
--
VDD
3.3V power pin
90
--
GND
Ground
91
--
VDD18
1.8V power pin
92
--
GND
Ground
93
I/O
AD[15]
PCI address data bus
94
I/O
AD[14]
PCI address data bus
95
--
VDD
3.3V power pin
96
--
GND
Ground
97
I/O
AD[13]
PCI address data bus
98
I/O
AD[12]
PCI address data bus
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 2.0
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